Viterbi decoder with the pipeline processing function

Claim 2

A Viterbi decoder with a pipeline processing function for decoding received code sequences transferred from an encoder, comprising: correlation determining means for receiving a code sequence and for calculating correlations between received code sequences and each of a plurality of predetermined code sequences; and first selecting means, operatively connected to receive said correlations, for selecting one of said predetermined code sequences as a maximum likelihood sequence, the selected one of said predetermined code sequences having the maximum correlation among said correlations, and for obtaining a decoded code sequence from said selected one of said predetermined code sequences, wherein said correlation determining means comprises: new correlation determining means for determining a new correlation based on a first received code sequence and a previously calculated correlation between a previously received code sequence and one of said predetermined code sequences; and comparing means for comparing, simultaneously with the determination of the new correlations, previously calculated correlations between the previously received code sequence and said pretermined code sequences, and for providing path selection data; second selecting means, operatively connected to said new correlation determining means and said comparing means, for selecting in response to said path selection data, one of said new correlations from said new correlation determining means, such that the selected new correlation has the maximum correlation among said new correlations applied to said second selecting means; said first selecting means selecting, in response to said selecting data, one of said predetermined code sequences as the maximum likelihood sequence with respect to the code sequence generated by the encoder.

Claim 3

A Viterbi decoder with a pipeline processing function for decoding received code sequences each comprising code units and being transferred from an encoder having a plurality of states, comprising: clock signal generator means for generating a clock signal having predetermined clock cycle periods; first correlation determing circuit means for obtaining, during each of said clock cycle periods, a plurality of first correlations (bm) between a unit of a received code sequence and a plurality of fixed units of predetermined code sequences, each fixed unit corresponding to a predetermined path from one state to a subsequent state of said encoder when said encoder generates one of said predetermined code sequences; second correlation determining means for obtaining, during each of said clock cycle periods, a plurality of second correlations (pm), each of said correlations being determined based on a corresponding one of said first correlations and at least two previously calculated second correlations, said previously calculated second correlations being calculated during a clock cycle period immediately preceeding the current clock cycle period; and first selecting means for selecting one of said predetermined code sequences, said selected predetermined code sequence having the maximum correlation of said plurality of second correlations, and for obtaining a decoded code sequence from said selected code sequence; wherein each of said second correlation determining includes comparing means for comparing, during each of said clock cycle periods, said previously calculated second correlations and for providing path selecting data, said path selecting data corresponding to the maximum correlation of said previously calculated second correlations, and being applied to said first selecting means, such that said first selecting means selects one of said predetermined code sequences in response to said path selecting data; adding means for adding, during each of said clock cycle periods, one of said first correlations (bm) to one of said previously calculated second correlations and for generating a new second correlation in accordance with the addition; second selecting means for selecting, in response to said path selecting data, one of said new second correlations, the selected new second correlation having the maximum correlation of said second correlations; and updating means for updating said previously calculated second correlations in accordance with said selected new second correlations and during a clock cycle period subsequent to the clock cycle period during which said previously calculated second correlations are compared simultaneously with the addition of said first correlations to said previously calculated second correlations.

Claim 4

A Viterbi decoder with a pipeline processing function for decoding received code sequences each comprising code units and being transferred from an encoder having a plurality of states, comprising: clock signal generator means for generating a clock signal having predetermined clock cycle periods; first correlation determing circuit means for obtaining, during each of said clock cycle periods, a plurality of first correlations (bm) between a unit of a received code sequence and a plurality of fixed units of predetermined code sequences, each fixed unit corresponding to a predetermined path from one state to a subsequent state of said encoder when said encoder generates one of said predetermined code sequences; second correlation determining means for obtaining, during each of said clock cycle periods, a plurality of second correlations (pm), each of said correlations being determined based on a corresponding one of said first correlations and at least two previously calculated second correlations, said previously calculated second correlations being calculated during a clock cycle period immediately preceeding the current clock cycle period; and first selecting means for selecting one of said predetermined code sequences, said selected predetermined code sequence having the maximum correlation of said plurality of second correlations, and for obtaining a decoded code sequence from said selected code sequence; wherein each of said second correlation determining includes comparing means for comparing, during each of said clock cycle periods, said previously calculated second correlations and for providing path selecting data, said path selecting data corresponding to the maximum correlation of said previously calculated second correlations, and being applied to said first selecting means, such that said first selecting means selects one of said predetermined code sequences in response to said path selecting data; adding means for adding, during each of said clock cycle periods, one of said first correlations (bm) to one of said previously calculated second correlations and for generating a new second correlation in accordance with the addition; second selecting means for selecting, in response to said path selecting data, one of said new second correlations, the selected new second correlation having the maximum correlation of said second correlations; and updating means for updating said previously calculated second correlations in accordance with said selected new second correlations and during a clock cycle period subsequent to the clock cycle period during which said previously calculated second correlations are compared simultaneously with the addition of said first correlations to said previously calculated second correlations.

Claim 5

A Viterbi decoder as set forth in claim 2, wherein said code units each comprise a received pair of symbols; said fixed units of said predetermined code sequences comprise four pairs of symbols (0, 0), (1, 1), (1, 0), and (0, 1); said first correlations correspond to branch metrics; and said first correlation determining means comprises first branch metric calculating means for calculating a first branch metric equal to a Hamming distance between said received pair of symbols and the first one of said fixed units (0, 0); second branch metric calculating means for calculating a second branch metric equal to a Hamming distance between said received pair of symbols and the second one of said fixed units (1, 1); a third branch metric calculating means for calculating a third branch metric equal to a Hamming distance between said received pair of symbols and the thrid one of said fixed units (1, 0); and fourth branch metric calculating means for calculating a fourth branch metric equal to a Hamming distance between said received pair of symbols and the fourth one of said fixed unit (0, 1).

Claim 6

A Viterbi decoder as set forth in claim 3, wherein said second correlations correspond to path metrics and each represents a cumulative correlation between said received code sequence and one of said predetermined code sequences, such that the path metric and the correlation vary inversely.

Claim 7

A Viterbi decoder as set forth in claim 4, wherein said encoder has a plurality of states and a set of allowable transitions between said states of said encoder, said branch metric calculating means each being associated with one of the allowable transitions, said encoder further comprising: four of said second correlation determining means respectively associated with four of said encoder states "00", "10", "01", and "11" and with respective ones of the allowable transitions, each of said second correlation determining means operatively connected to receive two branch metrics from two of said branch metric calculating means corresponding to the allowable transitions to the state associated with said second correlation determining means, and to receive two previously calculated path metrics from two of said second correlation determining means corresponding to the allowable transitions to the state associated with said second correlation determining means.

Claim 8

A Viterbi decoder as set forth in claim 5, wherein said updating means comprises: metric memory means, operatively connected through said second selecting means to said adding means, for storing said new path metric selected by said second selecting means in response to a clock signal generated by said clock signal generator means, said adding means and said comparing means cooperate to calculate said new path metric during a clock cycle period just prior to said new path metrics being stored in said metric memory means.