US4823346A
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Maximum likelihood decoder
Assignee: Hitachi Ltd
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Filing: 1987-04-16
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Granted: 1989-04-18
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Expires: 2007-04-16
Abstract
Abstract A maximum likelihood decoder for decoding a code from a signal transmitted through quadrature amplitude modulation of a code including a convolutional code can decode at high speed and high accuracy with a simple hardware configuration. In the maximum likelihood decoding of the convolutional code, the metric processing is not carried out for all of the possible paths and states but a smaller number of path(s) (metric(s)) and state(s) (metric(s)) are selected in a descending order to determine survival paths.
Inventors
- 👤 Naoya Kobayashi
- 👤 Makoto Ohnishi
- 👤 Yoshiro Kokuryo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:03
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/32; H04L27/34; H04L27/3405; H04L27/3416; H04L27/3427; H04L27/3438; H03; H03M; H03M13/00; H03M13/25; H03M13/37; H03M13/39; H03M13/41
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
A maximum likelihood decoder comprising: a path metric decision circuit for determining path metric of (an) input signal(s) against (a) reference signal(s); selection circuits for selecting n out of M (n<M) path metric determined by said path metric decision circuit in a descending order; first memories for storing m state metric selected in a descending order from M (m<M) state of metric before one symbol interval; first means for receiving the output of said selection circuits and the output of said first memories to determine a combination of states and paths to be operated; second means for adding, comparing and selecting against the m states and n paths determined by said first means; normalization means for normalizing the output of said second means and selecting the m state metric(s) at current time and storing the selected state metric(s) into said first memories; a path memory for storing paths connected to the current state metric(s) determined by said second means as survival paths; and a path tracing circuit for estimating a decoder output based on the survival paths stored in said path memory.
Claim 2
Dependent Claim
182 words
A maximum likelihood decoder comprising: a path metric decision circuit for determining path metric of (an) input signal(s) against (a) reference signal(s); selection circuits for selecting n out of M (n<M) path metric determined by said path metric decision circuit in a descending order; first memories for storing m state metric selected in a descending order from M (m<M) state of metric before one symbol interval; first means for receiving the output of said selection circuits and the output of said first memories to determine a combination of states and paths to be operated; second means for adding, comparing and selecting against the m states and n paths determined by said first means; normalization means for normalizing the output of said second means and selecting the m state metric(s) at current time and storing the selected state metric(s) into said first memories; a path memory for storing paths connected to the current state metric(s) determined by said second means as survival paths; and a path tracing circuit for estimating a decoder output based on the survival paths stored in said path memory.
Claim 3
Dependent Claim
19 words
A maximum likelihood decoder according to claim 1 wherein said M, m and n meet; 0≦m<M, 1≦n<M, and m+n≧2.
Claim 4
Dependent Claim
16 words
A maximum likelihood decoder according to claim 2 wherein M=8, and n=m=1, or m=0 and n=2.
Claim 5
Dependent Claim
130 words
A maximum likelihood decoder according to claim 1, further comprising: a domain decision circuit for receiving a signal produced by convolutionally coding only lower j bits out of k-bit information sequence (k≧2) into l (l>j) bits with non-converting i higher (i=k-j) bits to produce an (i+l)-bit convolutional code, and quadrature amplitude-modulating the convolutional code according to signal point mapping or constellation, dividing the two dimensional area of the signal point mapping into small domains, determining a small domain to which the received signal point belongs and supplying the received signal point and said domain to said path metric decision circuit; and higher i bit decoding means for decoding the i bits based on the information on the domain to which the received point belongs produced by said domain decision circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |