Patent US5445998A successfully refreshed from Google Patents.
US5445998A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for the global planarization of surfaces of semiconductor integrated circuits
Assignee: TDK Micronas GmbH
•
Filing: 1993-11-17
•
Granted: 1995-08-29
•
Expires: 2013-11-17
Abstract
Abstract A method for the global planarization of surfaces of semiconductor integrated circuits which involves etching back an auxiliary layer made of a dielectric with a single auxiliary photoresist step is disclosed.
Inventors
- 👤 Hans-Guenter Zimmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:37
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
153 words
A method for the global planarization of a surface of a semiconductor integrated circuit comprising the steps of: forming a pattern of conductive tracks (20) on the surface of a substrate (10); disposing a dielectric layer (30) of thickness d over the surface of the substrate (10); selectively disposing a photoresist layer over the dielectric layer (30) and patterning the photoresist layer to form a photoresist mask (40) in those areas between the conductive tracks (20) where the spacing between adjacent tracks is a multiple greater than the thickness, d, of the dielectric layer (30), taking into account alignment tolerances and optical resolution; selectively and anisotropically etching the dielectric layer (30) to uncover the conductive tracks (20) and the surface of the substrate (10) with spacers (35) being formed at the sides of the conductive tracks (20); stripping the photoresist without removing spacers (35); and planarizing the surface of the semiconductor integrated circuit.
Claim 2
Independent Claim
153 words
A method for the global planarization of a surface of a semiconductor integrated circuit comprising the steps of: forming a pattern of conductive tracks (20) on the surface of a substrate (10); disposing a dielectric layer (30) of thickness d over the surface of the substrate (10); selectively disposing a photoresist layer over the dielectric layer (30) and patterning the photoresist layer to form a photoresist mask (40) in those areas between the conductive tracks (20) where the spacing between adjacent tracks is a multiple greater than the thickness, d, of the dielectric layer (30), taking into account alignment tolerances and optical resolution; selectively and anisotropically etching the dielectric layer (30) to uncover the conductive tracks (20) and the surface of the substrate (10) with spacers (35) being formed at the sides of the conductive tracks (20); stripping the photoresist without removing spacers (35); and planarizing the surface of the semiconductor integrated circuit.
Claim 3
Dependent Claim
56 words
The method of claim 1 where between the step of forming an interconnection pattern of conductive tracks (20) on the surface of the substrate (10) and the step of disposing a dielectric layer (30) of thickness d over the surface of the substrate (10), a thin dielectric layer (31) is disposed for the purpose of preplanarization.
Claim 4
Dependent Claim
34 words
The method of claim 1 where in the step of disposing a dielectric layer (30) of thickness d over the surface of the substrate (10), the dielectric layer 30 is made of silicon dioxide.
Claim 5
Dependent Claim
34 words
The method of claim 2 where in the step of disposing a dielectric layer of thickness d over the surface of the substrate (10), dielectric layers 30 and 31 are made of silicon dioxide.
Claim 6
Dependent Claim
33 words
The method of claim 1 where in the step of disposing a dielectric layer of thickness d over the surface of the substrate (10), the dielectric layer 30 is made of silicate glass.
Claim 7
Dependent Claim
34 words
The method of claim 2 where in the step of disposing a dielectric layer of thickness d over the surface of the substrate (10), dielectric layers 30 and 31 are made of silicate glass.
Claim 8
Dependent Claim
111 words
An improvement in a method for planarizing an integrated circuit substrate (10) having a plurality of structures (20) with vertical height laterally disposed thereacross comprising the steps of: selectively forming nonconductive open-area spacers (36) between said plurality of structures (20); simultaneously forming nonconductive spacers (35) contiguously adjacent to said plurality of structures (20), where the lateral distance between adjacent ones of said plurality Of structures (20) is a multiple of the vertical thickness of said spacers (35, 36); and planarizing said plurality of structures (20), contiguous spacers (35) and open-area spacers (36) to provide a substantially planar surface over said plurality of structures (20), contiguous spacers (35) and open-area spacers (36).
Claim 9
Dependent Claim
111 words
An improvement in a method for planarizing an integrated circuit substrate (10) having a plurality of structures (20) with vertical height laterally disposed thereacross comprising the steps of: selectively forming nonconductive open-area spacers (36) between said plurality of structures (20); simultaneously forming nonconductive spacers (35) contiguously adjacent to said plurality of structures (20), where the lateral distance between adjacent ones of said plurality Of structures (20) is a multiple of the vertical thickness of said spacers (35, 36); and planarizing said plurality of structures (20), contiguous spacers (35) and open-area spacers (36) to provide a substantially planar surface over said plurality of structures (20), contiguous spacers (35) and open-area spacers (36).
Claim 10
Dependent Claim
44 words
The improvement of claim 7 where said step of selectively forming nonconductive open-area spacers (36) between said plurality of structures (20) is performed depending upon layer thickness of said structures (20) used on said substrate (10) and geometry of said plurality of structures (20).
Claim 11
Dependent Claim
52 words
The improvement of claim 7 where said step of selectively forming nonconductive open-area spacers (36) between said plurality of structures (20) is performed depending upon alignment accuracy and optical properties of photolithographic exposure equipment used to define said structures (20) on said substrate (10) and geometry of said plurality of structures (20).
References Cited (Backward Citations)
EP0054164A1
Cited
US4505029A
Cited
EP0084635A2
Cited
US4634496A
Cited
US4662064A
Cited
US4962060A
Cited
EP0405850A2
Cited
EP0416165A1
Cited
US5229325A
Cited
US5262352A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |