US4505029A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with built-up low resistance contact
Assignee: Fairchild Semiconductor Corp
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Filing: 1983-07-08
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Granted: 1985-03-19
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Expires: 2003-07-08
Abstract
Abstract A semiconductor device having particularly low resistance connection to a portion thereof carrying substantial current is described. First and second electrodes are provided on a major surface of the semiconductor, the first electrode providing lateral contact to a control region of the semiconductor device; the second electrode providing low impedance vertical contact to the high current carrying region. A conductive plate is supported between upstanding spaced apart portions of the second electrode and is thereby vertically spaced apart from the first electrode.
Inventors
- 👤 King Owyang
- 👤 Leonard Stein, deceased
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:02
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10W72/00; H10W72/01; H10W72/012; H10W72/019; H10W72/20; H10W72/251; H10W72/252; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
215 words
A method for making a built-up metal contact for a controllable high current semiconductor device which contact includes a vertically conducting portion on a high current carrying portion of said device and a laterally conducting portion on a low current carrying control portion of said device, each of said high and low current carrying portions having lateral configuration which includes fingers interdigitated with the fingers of the other current carrying portion; said method comprising the steps of: simultaneously forming first and second laterally spaced apart metal layers on said high and low current carrying portions respectively, each of said metal layers conforming substantially to said lateral configuration of the underlying current carrying portion of said device; forming a curable insulative dielectric dual-layer substantially fully covering both of said metal layers; exposing an upper surface substantially throughout the complete lateral configuration of said first metal layer; forming a layer of barrier material on said exposed upper surface which fully covers said surface; forming a layer of solderable material on said layer of barrier material substantially fully covering said barrier material; forming a layer of solder on said layer of solderable material substantially fully covering said solderable material; and attaching a metal plate to said layer of solder throughout the full lateral configuration of said solder layer.
Claim 2
Independent Claim
215 words
A method for making a built-up metal contact for a controllable high current semiconductor device which contact includes a vertically conducting portion on a high current carrying portion of said device and a laterally conducting portion on a low current carrying control portion of said device, each of said high and low current carrying portions having lateral configuration which includes fingers interdigitated with the fingers of the other current carrying portion; said method comprising the steps of: simultaneously forming first and second laterally spaced apart metal layers on said high and low current carrying portions respectively, each of said metal layers conforming substantially to said lateral configuration of the underlying current carrying portion of said device; forming a curable insulative dielectric dual-layer substantially fully covering both of said metal layers; exposing an upper surface substantially throughout the complete lateral configuration of said first metal layer; forming a layer of barrier material on said exposed upper surface which fully covers said surface; forming a layer of solderable material on said layer of barrier material substantially fully covering said barrier material; forming a layer of solder on said layer of solderable material substantially fully covering said solderable material; and attaching a metal plate to said layer of solder throughout the full lateral configuration of said solder layer.
Claim 3
Dependent Claim
46 words
The method of claim 1 wherein forming said first and second metal layers comprises forming a layer of metal on a surface of said device and selectively removing portions thereof to leave said first and second layers aligned with said high and low current carrying portions.
Claim 4
Dependent Claim
69 words
The method of claim 2 wherein forming said insulative dielectric dual-layer comprises: (a) forming a thin lower layer of a dielectric material on both of said metal layers; (b) curing said lower layer; (c) forming an upper layer of said dielectric material on said lower layer; (d) curing said upper layer; and (e) fully curing said lower and upper layers at a temperature sufficient to form a homogeneous layer.
Claim 5
Dependent Claim
33 words
The method of claim 3 wherein exposing said upper surface of said first metal layer comprises masking desired portions of said dielectric layer and etching to remove the portions overlying said upper surface.
Claim 6
Dependent Claim
54 words
The method of claim 1 wherein forming said layer of solderable material comprises: forming a first layer of solderable material and forming a layer of protective material on said layer of solderable material; removing said layer of protective material and applying a second layer of solderable material on said first layer of solderable material.
Claim 7
Dependent Claim
36 words
The method of claim 5 wherein said protective layer and said first layer of solderable material are formed by sputtering and said second layer of solderable material and said layer of solder are formed by plating.
Claim 8
Dependent Claim
32 words
The method of claim 1 wherein forming said layer of solder comprises separately forming consecutive layers of the components of an alloy solder and heating said layers to form said solder layer.
Claim 9
Dependent Claim
43 words
The method of claim 1 wherein attaching said metal plate comprises placing said plate in contact with said layer of solder throughout the lateral configuration of said solder layer, and heating said device to solder said plate to the remainder of said device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-18 | 1988-09-17 | 1989-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-18 | 1992-09-17 | 1993-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-18 | 1996-09-17 | 1997-03-19 | $7700.00 | Window Closed / Lapsed |