Semiconductor memory device having means for monitoring bias voltage

Claim 2

A semiconductor memory device comprising: a power supply terminal; a circuit ground; a plurality of memory cells for storing data; means connected between the power supply terminal and the circuit ground and having a depletion-type FET and an intrinsic-type FET for generating a bias voltage to be applied to the memory cells; and connecting/applying means for connecting the generating means to an external measuring device and for applying the bias voltage to the external measuring device.

Claim 3

A semiconductor memory device comprising to claim 1, wherein said connecting/applying means includes a metal pad.

Claim 4

A semiconductor memory device according to claim 1, wherein the memory cells include floating gate FETs.

Claim 5

A semiconductor memory device according to claim 1, further comprising a load circuit and a switching transistor which are arranged between the bias voltage generating means and the plurality of memory cells.

Claim 6

A semiconductor memory device according to claim 1, further comprising: means for selecting one signal from a plurality of signals to supply to the monitor means.

Claim 7

A semiconductor memory device comprising:. a power supply terminal; a circuit ground; a plurality of memory cells for storing data; means, connected between the power supply terminal and the circuit ground, including a switching transistor, a depletion-type FET, and an intrinsic-type FET for generating a bias voltage to be applied to the memory cells; and connecting/applying means for connecting the bias voltage generating means to an external measuring device and for applying the bias voltage to the external measuring device.

Claim 8

A semiconductor memory device comprising:. a power supply terminal; a circuit ground; a plurality of memory cells for storing data; means, connected between the power supply terminal and the circuit ground, including a switching transistor, a depletion-type FET, and an intrinsic-type FET for generating a bias voltage to be applied to the memory cells; and connecting/applying means for connecting the bias voltage generating means to an external measuring device and for applying the bias voltage to the external measuring device.

Claim 9

A semiconductor memory device comprising: a power supply terminal; a circuit ground; a plurality of memory cells for storing data; means connected between the power supply terminal and the circuit ground for generating a bias voltage to be applied to the memory cells; connecting/applying means for connecting the generating means to an external measuring device and for applying the bias voltage to the external measuring device; and a resistor and capacitor which are arranged between the bias voltage generating means and a monitor means.

Claim 10

A semiconductor memory device comprising: a power supply terminal; a circuit ground; a plurality of memory cells for storing data; means connected between the power supply terminal and the circuit ground for generating a bias voltage to be applied to the memory cells; connecting/applying means for connecting the generating means to an external measuring device and for applying the bias voltage to the external measuring device; and a resistor and capacitor which are arranged between the bias voltage generating means and a monitor means.

Claim 11

A semiconductor memory device formed on a semiconductor chip, comprising: a power supply terminal formed on the chip; a circuit ground formed on the chip; a plurality of memory cells formed on the chip, for storing data; a depletion-type FET having two ends, a first end being connected to the power supply terminal; an intrinsic-type FET having two ends, a first end being connected to a second end of the depletion-type FET, and a second end being connected to the circuit ground; and monitor means, connected to the second end of the depletion-type FET, for measuring the drain potential of at least one of the plurality of memory cells.

Claim 12

A semiconductor memory device formed on a semiconductor chip, comprising: a power supply terminal formed on the chip; a circuit ground formed on the chip; a plurality of memory cells formed on the chip, for storing data; a depletion-type FET having two ends, a first end being connected to the power supply terminal; an intrinsic-type FET having two ends, a first end being connected to a second end of the depletion-type FET, and a second end being connected to the circuit ground; and monitor means, connected to the second end of the depletion-type FET, for measuring the drain potential of at least one of the plurality of memory cells.

Claim 13

A semiconductor memory device according to claim 8, wherein the monitor means includes a metal pad.

Claim 14

A semiconductor memory device according to claim 8, wherein the plurality of memory cells include floating gate FETs.