US5440701A — For shortening an instruction code length

Claim 1

Independent Claim 207 words

A data processing unit for compressing an instruction code size comprising: m data registers for holding data; n address registers for holding addresses; means for decoding an instruction, said decoding means decoding an 8-bit instruction comprising a code that designates at least one operation, a log 2 m-bit register-addressing code used to address at least one of said m data registers, and a log 2 n-bit register-addressing code used to address at least one of said n address registers; means for executing an instruction by computing and transferring data in accordance with a signal decoded by said decoding means, said executing means being connected to said one data register and said one address register, and said executing means transferring data between a memory addressed by said one address register and said one data register; and means for detecting whether the two register addressing codes contained in an 8-bit instruction match or not, said detecting means being connected to said decoding means to output a detection result, wherein said executing means carries out a first process when said detecting means detects a match between said two register-addressing codes, and carries out a second process when said detecting means does not detect a match between said two register-addressing codes.

Claim 2

Dependent Claim 207 words

A data processing unit for compressing an instruction code size comprising: m data registers for holding data; n address registers for holding addresses; means for decoding an instruction, said decoding means decoding an 8-bit instruction comprising a code that designates at least one operation, a log 2 m-bit register-addressing code used to address at least one of said m data registers, and a log 2 n-bit register-addressing code used to address at least one of said n address registers; means for executing an instruction by computing and transferring data in accordance with a signal decoded by said decoding means, said executing means being connected to said one data register and said one address register, and said executing means transferring data between a memory addressed by said one address register and said one data register; and means for detecting whether the two register addressing codes contained in an 8-bit instruction match or not, said detecting means being connected to said decoding means to output a detection result, wherein said executing means carries out a first process when said detecting means detects a match between said two register-addressing codes, and carries out a second process when said detecting means does not detect a match between said two register-addressing codes.

Claim 3

Dependent Claim 17 words

The apparatus of claim 1 wherein an instruction containing immediate data is processed in said first process.

Claim 4

Dependent Claim 23 words

The apparatus of claim 2 wherein a register is addressed and a content thereof is compared with the immediate data at said instruction.

Claim 5

Dependent Claim 20 words

The apparatus of claim 2 wherein a register is addressed and the immediate data are transferred thereto at said instruction.

Claim 6

Dependent Claim 27 words

The apparatus of claim 1 wherein a content of a register addressed by said instruction is shifted to the left by one bit in said second process.

Claim 7

Dependent Claim 21 words

The apparatus of claim 1 wherein a content of a register addressed by said instruction is cleared in said second process.

Claim 8

Dependent Claim 117 words

A data processing apparatus for executing an 8-bit instruction code, the instruction code comprising a leading bit, three bits which designate any of 8 different types of operation instructions, and two 2-bit register addressing codes, the apparatus comprising: an instruction buffer for outputting the instruction code; an instruction register for receiving and holding the instruction code; determining means connected to the instruction register for determining whether the two 2-bit register addressing codes in the 8-bit instruction code are the same; and an instruction decoder, connected to the instruction register and the determining means, for decoding the instruction code and for outputting a control signal, the control signal being based upon the determination made by the determining means.

Claim 9

Dependent Claim 117 words

A data processing apparatus for executing an 8-bit instruction code, the instruction code comprising a leading bit, three bits which designate any of 8 different types of operation instructions, and two 2-bit register addressing codes, the apparatus comprising: an instruction buffer for outputting the instruction code; an instruction register for receiving and holding the instruction code; determining means connected to the instruction register for determining whether the two 2-bit register addressing codes in the 8-bit instruction code are the same; and an instruction decoder, connected to the instruction register and the determining means, for decoding the instruction code and for outputting a control signal, the control signal being based upon the determination made by the determining means.

Claim 10

Dependent Claim 158 words

A data processing apparatus for minimizing the sizes of programs by using relatively short instruction word lengths, the apparatus comprising: an instruction register for holding an instruction code, the instruction code comprising an operation code that designates an operation, a data register code used to address a data register from a plurality of data registers, and an address register code used to address an address register from a plurality of address registers; and means for determining whether the values of the data register code and address register code match, and for decoding the instruction code, the decoding means interpreting the operation code differently depending on whether a match is found, the decoding means having means for outputting a control signal designating a first type of instruction when the values of the two register designation codes match, and for outputting a control signal designating a second type of operation when the values of the two registers do not match.

Claim 11

Dependent Claim 158 words

A data processing apparatus for minimizing the sizes of programs by using relatively short instruction word lengths, the apparatus comprising: an instruction register for holding an instruction code, the instruction code comprising an operation code that designates an operation, a data register code used to address a data register from a plurality of data registers, and an address register code used to address an address register from a plurality of address registers; and means for determining whether the values of the data register code and address register code match, and for decoding the instruction code, the decoding means interpreting the operation code differently depending on whether a match is found, the decoding means having means for outputting a control signal designating a first type of instruction when the values of the two register designation codes match, and for outputting a control signal designating a second type of operation when the values of the two registers do not match.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-08-07	1999-02-06	1999-08-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-08-07	2003-02-06	2003-08-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-08-07	2007-02-06	2007-08-08	$7700.00	Window Closed / Lapsed

For shortening an instruction code length

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