Variable length instruction decoding apparatus having cross coupled first and second microengines

Claim 2

An instruction preparation unit of a computer system comprising: register means for storing a variable length instruction; first microengine means coupled to said register means for decoding a first portion of said instruction and decoding a second portion for said instruction having said second portion; second microengine means, coupled to said register means and having an input coupled to a first output of said first microengine means and a first output of said second microengine means coupled to an input of said first microengine means, for decoding said first portion of said instruction to generate signals for a local computer instruction; calculator means, having inputs coupled to a second output of said first and second microengine means and to outputs of said register means and having a first output coupled to an input of said first microengine means, for performing calculations to generate signals for said local computer instruction; and means coupled to a second output signal of said calculator means and a third output of said second microengine means for selecting one or more portions of decoded signals from said third output of said second microengine means and/or one or more portions of said calculator means second output signal in response to control signals generated by said first microengine means to form said local computer instruction.

Claim 3

The instruction preparation unit recited in claim 1 wherein: said first portion of the instruction comprises an opcode field and for said instruction having said second portion, said second portion comprises at least one specifier field.

Claim 4

The instruction preparation unit recited in claim 1 wherein: said first microengine and said second microengine being interconnected whereby said first output of said first microengine being coupled to said input of said second microengine and said first output of said second microengine being coupled to said input of said first micorengine, for conditionally controlling and providing said input to each other of said first microengine and second microengine.

Claim 5

The instruction preparation unit recited in claim 2 wherein: said first microengine means receives an address via a multiplexer means having a plurality of address source inputs including address sources from said register means and said second microengine means.

Claim 6

The instruction preparation unit recited in claim 4 wherein: said multiplexer means comprises a logic selector for selecting one of said plurality of address sources in accordance with control signals received from said first microengine, said second microengine and said opcode portion of said instruction word.

Claim 7

The instruction preparation unit recited in claim 1 wherein: said first microengine comprises a control store means; and an output from said control store means is stored in a first microengine register means.

Claim 8

The instruction preparation unit recited in claim 1 wherein: said second microengine comprises a control store means; and an output from said control store means is stored in a second microengine register means.

Claim 9

An instruction preparation unit of a computer system comprising: register means for storing a variable length instruction; first microengine means coupled to said register means for decoding a first portion of said instruction and a second portion for said instruction having said second portion; second microengine means, coupled to said register means and having an input coupled to a first output of said first microengine means and a first output of said second microengine means coupled to an input of said first microengine means, for decoding said first portion of said instruction to generate signals for a local computer instruction; calculator means, having inputs coupled to a second output of said first and second microengine means and to outputs of said register means and having a first output coupled to an input of said first microengine means, for performing calculations to generate signals for said local computer instruction; means coupled to a second output signal of said calculator means and a third output of said second microengine means for selecting one or more portions of decoded signals from said third output of said second microengine means and/or one or more portions of said calculator means second output signal in response to control signals generated by said first microengine means to form said local computer instruction; and prefetch control means coupled to said register means output for providing an instruction stream to said instruction storing register means by obtaining a next variable length instruction field while a previously obtained instruction field is being processed.

Claim 10

An instruction preparation unit of a computer system comprising: register means for storing a variable length instruction; first microengine means coupled to said register means for decoding a first portion of said instruction and a second portion for said instruction having said second portion; second microengine means, coupled to said register means and having an input coupled to a first output of said first microengine means and a first output of said second microengine means coupled to an input of said first microengine means, for decoding said first portion of said instruction to generate signals for a local computer instruction; calculator means, having inputs coupled to a second output of said first and second microengine means and to outputs of said register means and having a first output coupled to an input of said first microengine means, for performing calculations to generate signals for said local computer instruction; means coupled to a second output signal of said calculator means and a third output of said second microengine means for selecting one or more portions of decoded signals from said third output of said second microengine means and/or one or more portions of said calculator means second output signal in response to control signals generated by said first microengine means to form said local computer instruction; and prefetch control means coupled to said register means output for providing an instruction stream to said instruction storing register means by obtaining a next variable length instruction field while a previously obtained instruction field is being processed.

Claim 11

The instruction preparation unit recited in claim 8 wherein: said first portion of the instruction comprises an opcode field and for said instruction having said second portion, said second portion comprises at least one specifier field.

Claim 12

The instruction preparation unit recited in claim 8 wherein: said first microengine and said second microengine being interconnected whereby said first output of said first microengine being coupled to said input of said second microengine and said first output of said second microengine being coupled to said input of said first microengine, for conditionally controlling and providing said input to each other of said first microengine and second microengine.

Claim 13

The instruction preparation unit recited in claim 9 wherein: said first microengine means receives an address via a multiplexer means having a plurality of address source inputs including address sources from said register means and said second microengine means.

Claim 14

The instruction preparation unit recited in claim 11 wherein: said multiplexer means comprises a logic selector for selecting one of said plurality of address sources in accordance with control signals received from said first microengine, said second microengine and said opcode portion of said instruction word.

Claim 15

The instruction preparation unit recited in claim 8 wherein: said first microengine comprises a control store means; and an output from said control store means is stored in a first microengine register means.

Claim 16

The instruction preparation unit recited in claim 8 wherein: said second microengine comprises a control store means; and an output from said control means is stored in a second microengine register means.

Claim 17

A pipeline computer system comprising: memory means for storing instructions and data; instruction preparation means coupled to said memory means for converting a variable length instruction into a local computer instruction; operand handler means coupled to said instruction preparation means for transferring information to and from said memory means and resolving pipeline timing conflicts within said computer system; execution means coupled to said operand handler means for performing logical and arithmetic operations; bus means interconnecting said memory means, said operand handler means and said execution means for transferring address and data information to and from each of said memory means, said operand handler means and said execution means; said instruction preparation means further comprising: register means for storing said variable length instruction; first microengine means coupled to said register means for decoding a first portion of said variable length instruction and decoding a second portion for said variable length instruction having said second portion; second microengine means coupled to said register means and having an input coupled to a first output of said first microengine means and a first output of said second microengine means coupled to an input of said first microengine means for decoding said first portion of said variable length instruction to generate signals for a local computer instruction; calculator means, having inputs coupled to a second output of said first and second microengine means and to outputs of said register means and having a first output coupled to an input of said first microengine means, for performing calculations to generate signals for said local computer instruction; and means coupled to a second output signal of said calculator means and a third output of said second microengine means for selecting one or more portions of decoded signals from said third output of said second microengine means and/or one or more portions of said calculator means second output signal in response to control signals generated by said first microengine means to form said local computer instruction.

Claim 18

A pipeline computer system comprising: memory means for storing instructions and data; instruction preparation means coupled to said memory means for converting a variable length instruction into a local computer instruction; operand handler means coupled to said instruction preparation means for transferring information to and from said memory means and resolving pipeline timing conflicts within said computer system; execution means coupled to said operand handler means for performing logical and arithmetic operations; bus means interconnecting said memory means, said operand handler means and said execution means for transferring address and data information to and from each of said memory means, said operand handler means and said execution means; said instruction preparation means further comprising: register means for storing said variable length instruction; first microengine means coupled to said register means for decoding a first portion of said variable length instruction and decoding a second portion for said variable length instruction having said second portion; second microengine means coupled to said register means and having an input coupled to a first output of said first microengine means and a first output of said second microengine means coupled to an input of said first microengine means for decoding said first portion of said variable length instruction to generate signals for a local computer instruction; calculator means, having inputs coupled to a second output of said first and second microengine means and to outputs of said register means and having a first output coupled to an input of said first microengine means, for performing calculations to generate signals for said local computer instruction; and means coupled to a second output signal of said calculator means and a third output of said second microengine means for selecting one or more portions of decoded signals from said third output of said second microengine means and/or one or more portions of said calculator means second output signal in response to control signals generated by said first microengine means to form said local computer instruction.

Claim 19

The pipeline computer system recited in claim 15 wherein: said first portion of the variable length instruction stored in said register means of said instruction preparation means comprises an opcode field and for said variable length instruction having said second portion, said second portion comprises at least one specifier field.

Claim 20

The pipeline computer system recited in claim 15 wherein: said first microengine and said second microengine being interconnected whereby said firs output of said first microengine being coupled to said input of said second microengine and said first output of said second microengine being coupled to said input of said first microengine, for conditionally controlling and providing said input to each other of said first microengine and second microengine.

Claim 21

The pipeline computer system recited in claim 15 wherein: said instruction preparation means further comprises a prefetch control means coupled to said variable length instruction storing register means for providing an instruction stream to said instruction preparation means by obtaining a next variable length instruction field from said memory means while a previously obtained instruction field is being processed.

Claim 22

The pipeline computer system recited in claim 15 wherein: said first microengine of said instruction preparation means comprises a control store means; and an output from said control store means is stored in a first microengine register means.

Claim 23

The pipeline computer system recited in claim 15 wherein: said second microengine of said instruction preparation means comprises a control store means; and an output from said control store means is stored in a second microengine register means.

Claim 26

The method recited in claim 21 wherein: said step of decoding said first portion of said variable length instruction comprises decoding an opcode field, and decoding said second portion of said variable length instruction having said second portion comprises decoding at least one specifier field.

Claim 29

The method recited in claim 23 wherein: said step of decoding said first portion of said variable length instruction comprises decoding an opcode field, and for said variable length instruction having said second portion comprises decoding at least one specifier field.