Control state sequencer

Claim 2

A control state sequencer for use with a microprocessor having a processing unit for processing instructions comprised of a predetermined sequence of control states, comprising: a first ROM array, having a plurality of input lines each corresponding to a control state, programmed to provide, in response to an input line being enabled, the control state which corresponds to the input line which is enabled; a first PLA having a plurality of input lines for receiving an instruction code representative of an instruction and for receiving a current control state of the represented instruction, and having a plurality of output lines coupled to the input lines of the first ROM array; wherein the first PLA is programmed to enable the input line of the first ROM array which corresponds to a next control state, wherein the next control state is a control state which follows the current control state in the predetermined sequence of control states of said represented instruction, wherein the first PLA provides a load instruction register signal in response to receiving the last control state in the predetermined sequence of control states of the represented instruction, and wherein the first PLA enables an input line of the first ROM array which corresponds to an intermediate control state, said intermediate control state for preparing the processing unit to begin processing another instruction; and latch means for receiving the next control state from the first ROM array and for providing the current control state to the first PLA and to the processing unit in response to a clock signal.

Claim 3

A control state sequencer for use with a microprocessor having a processing unit for processing instructions comprised of a predetermined sequence of control states, comprising: a first ROM array, having a plurality of input lines each corresponding to a control state, programmed to provide, in response to an input line being enabled, the control state which corresponds to the input line which is enabled; a first PLA having a plurality of input lines for receiving an instruction code representative of an instruction and for receiving a current control state of the represented instruction, and having a plurality of output lines coupled to the input lines of the first ROM array, wherein the first PLA is programmed to enable the input line of the first ROM array which corresponds to a next control state, wherein the next control state is a control state which follows the current control state in the predetermined sequence of control states of said represented instruction; an initial-state ROM array, having a plurality of input lines, each corresponding to an initial control state of an instruction, programmed to provide to the first PLA, in response to an input line being enabled, the initial control state which corresponds to the input line which is enabled; and an initial-state PLA having a plurality of input lines coupled to the input lines of the first PLA for receiving the instruction code representative of the instruction, and a plurality of output lines coupled to the input lines of the initial-state ROM array, wherein the initial-state PLA is programmed to enable the input line of the initial-state ROM array which corresponds to the initial control state of the instruction in response to receiving the instruction code and an instruction enable signal.

Claim 4

A control state sequencer for use with a microprocessor having a processing unit for processing instructions comprised of a predetermined sequence of control states, comprising: a first ROM array, having a plurality of input lines each corresponding to a control state, programmed to provide, in response to an input line being enabled, the control state which corresponds to the input line which is enabled; a first PLA having a plurality of input lines for receiving an instruction code representative of an instruction and for receiving a current control state of the represented instruction, and having a plurality of output lines coupled to the input lines of the first ROM array, wherein the first PLA is programmed to enable the input line of the first ROM array which corresponds to a next control state, wherein the next control state is a control state which follows the current control state in the predetermined sequence of control states of said represented instruction; an initial-state ROM array, having a plurality of input lines, each corresponding to an initial control state of an instruction, programmed to provide to the first PLA, in response to an input line being enabled, the initial control state which corresponds to the input line which is enabled; and an initial-state PLA having a plurality of input lines coupled to the input lines of the first PLA for receiving the instruction code representative of the instruction, and a plurality of output lines coupled to the input lines of the initial-state ROM array, wherein the initial-state PLA is programmed to enable the input line of the initial-state ROM array which corresponds to the initial control state of the instruction in response to receiving the instruction code and an instruction enable signal.

Claim 5

The control state sequencer of claim 2 further comprising: latch means coupled to the first ROM array for receiving the next control state from the first ROM array and for providing the current control state to the first PLA and to the processing unit.

Claim 6

The control state sequencer of claim 3 wherein the latch means is further characterized as providing the next control state to the first PLA and the processing unit in response to a clock signal.

Claim 7

The control state sequencer of claim 4 wherein the latch means is further characterized as coupled to the initial-state ROM array for receiving the initial clock state when provided thereby, and then providing said initial clock state to the processing unit and the first PLA.