Image reduction system

Claim 2

Image reduction apparatus for deleting portions of image representations, comprising: storage means for storage of information used to form an image; output means coupled to said storage means for outputting image information to a utilizing device; data input means for supplying data to be entered into said storage means; data induction means for causing the selective elimination of data to produce a reduced data image representation; first means controlled by said data reduction means to cause a selective first elimination of data during data storage in said storage means; and second means controlled by said data reduction means to cause a selective second elimination of data during transfer of data from said storage means to said output means.

Claim 3

Image reduction apparatus for deleting portions of image representations, comprising: storage means for storage of information used to form an image; output register means coupled to said storage means for outputting data groups of image information to a utilizing device; data input means for supplying data in a series of segments to be entered into said storage means; address selector means synchronized in time with said data input means for determining addresses in the storage means into which segments of data from the data input means are entered and from which segments of data are read; data reduction means for causing portions of the data from the data input means to be deleted from the image information output from the output register means; write address counter means controlled by the data reduction means and coupled to the address selector means to provide write addresses to the address selector means and to cause one of a selected number of addresses to be repeated, thereby causing one of the data segments from the data input means to be eliminated from the storage means for each address which is repeated; and output sequencer means controlled by said data reduction means and coupled to said output register means to cause one of a selected number of said data groups of image information to be eliminated.

Claim 4

Image reduction apparatus for deleting portions of image representations, comprising: storage means for storage of information used to form an image; output register means coupled to said storage means for outputting data groups of image information to a utilizing device; data input means for supplying data in a series of segments to be entered into said storage means; address selector means synchronized in time with said data input means for determining addresses in the storage means into which segments of data from the data input means are entered and from which segments of data are read; data reduction means for causing portions of the data from the data input means to be deleted from the image information output from the output register means; write address counter means controlled by the data reduction means and coupled to the address selector means to provide write addresses to the address selector means and to cause one of a selected number of addresses to be repeated, thereby causing one of the data segments from the data input means to be eliminated from the storage means for each address which is repeated; and output sequencer means controlled by said data reduction means and coupled to said output register means to cause one of a selected number of said data groups of image information to be eliminated.

Claim 5

The apparatus of claim 2 in which said data groups comprise lines of image information.

Claim 6

The apparatus of claim 2 in which said segments comprise a plurality of characters in corresponding positions in a plurality of image lines.

Claim 7

The apparatus of claim 2 in which the data reduction means comprises reduction latch means for receiving and maintaining image reduction data and reduction counter means controlled by the reduction latch means for generating a count representative of the amount of the image reduction, and transmitting said count to the write address counter means for controlling write address generation.

Claim 8

The apparatus of claim 2 in which the storage means includes first and second buffer means; associated first and second data selection means; and gating means, whereby data can be input to one of said first and second buffer means while data is being read out of the other of said buffer means through said associated data selection means and applied to said output register means through said gating means.

Claim 9

The apparatus of claim 6 in which said gating means is an OR gate.

Claim 10

The apparatus of claim 6, also including input sequencer means for selecting which of the first and second buffer means is to be written into with data from the data input means, and which of the first and second buffer means is to be read out through its associated data selection means.

Claim 11

The apparatus of claim 8, in which the write address counter means also includes capacity count means coupled to the input sequencer means to control the input sequencer means to cause said input sequencer means to switch the first or second buffer means from a mode in which data is being written into it to a mode in which data is being read from it when the storage capacity of said buffer means is reached.

Claim 12

The apparatus of claim 9, in which the data reduction means also includes height code preset means which controls the write address counter means to cause the capacity count means to commence count at a value other than zero when a reduced image representation is to be provided by the apparatus.

Claim 13

The apparatus of claim 8, also including run length counter means coupled to the input sequencer means for controlling the number of times that the same segment of data from the data input means is stored in the storage means.

Claim 14

The apparatus of claim 2, also including read address counter means coupled to the address selector means and the output sequencer means to provide sequential addresses to the address selector means to cause stored data to be read from the storage means at those addresses.

Claim 15

Image reduction apparatus for deleting portions of image representations, comprising: storage means for storage of information used to form an image; output register means coupled to said storage means for outputting lines of image information to a utilizing device; data input means for supplying data in a series of segments to be entered into said storage means; address selector means synchronized in time with said data input means for determining addresses in the storage means into which segments of data from the data entry means are entered and from which segments of data are read; reduction latch means for receiving and maintaining image reduction data; reduction counter means controlled by the reduction latch means for generating a count representative of the amount of the image reduction, and transmitting said count to the write address counter means for controlling write address generation; write address counter means controlled by the reduction counter means and coupled to the address selector means to provide write addresses to the address selector means to cause certain predetermined addresses to be repeated, thereby causing one of the data segments from the data input means to be eliminated from the storage means for each address which is repeated; output sequencer means controlled by the reduction latch means and coupled to said output register means to cause selected lines of image information to be eliminated, and read address counter means coupled to the address selector means and the output sequencer means to provide sequential addresses to the address selector means to cause stored data to be read from the storage means at those addresses.

Claim 16

Image reduction apparatus for deleting portions of image representations, comprising: storage means for storage of information used to form an image; output register means coupled to said storage means for outputting lines of image information to a utilizing device; data input means for supplying data in a series of segments to be entered into said storage means; address selector means synchronized in time with said data input means for determining addresses in the storage means into which segments of data from the data entry means are entered and from which segments of data are read; reduction latch means for receiving and maintaining image reduction data; reduction counter means controlled by the reduction latch means for generating a count representative of the amount of the image reduction, and transmitting said count to the write address counter means for controlling write address generation; write address counter means controlled by the reduction counter means and coupled to the address selector means to provide write addresses to the address selector means to cause certain predetermined addresses to be repeated, thereby causing one of the data segments from the data input means to be eliminated from the storage means for each address which is repeated; output sequencer means controlled by the reduction latch means and coupled to said output register means to cause selected lines of image information to be eliminated, and read address counter means coupled to the address selector means and the output sequencer means to provide sequential addresses to the address selector means to cause stored data to be read from the storage means at those addresses.

Claim 17

The apparatus of claim 13 in which the storage means includes first and second buffer means; associated first and second data selection means; and gating means, whereby data can be input to one of said first and second buffer means while data is being read out of the other of said buffer means through said associated data selection means and applied to said output register means through said gating means.

Claim 18

The apparatus of claim 14 in which said gating means is an OR gate.

Claim 19

The apparatus of claim 14, also including input sequencer means for selecting which of the first and second buffer means is to be written into with data from the data input means, and which of the first and second buffer means is to be read out through its associated data selection means.

Claim 20

The apparatus of claim 16, in which the write address counter means also includes capacity count means coupled to the input sequencer means to control the input sequencer means to cause said input sequencer means to switch the first or second buffer means from a mode in which data is being written into it to a mode in which data is being read from it when the storage capacity of said buffer means is reached.

Claim 21

The apparatus of claim 17, in which the data reduction means also includes height code preset means which controls the write address counter means to cause the capacity count means to commence count at a value other than zero when a reduced image representation is to be provided by the apparatus.

Claim 22

The apparatus of claim 16, also including run length counter means coupled to the input sequencer means for controlling the number of times that the same segment of data from the data input means is stored in the storage means.