Patent CH372880A successfully refreshed from Google Patents.
US4432056A
Expired / Lapsed
US
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Programmable electronic computer
Assignee: Canon Inc
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Filing: 1983-06-28
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Granted: 1984-02-14
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Expires: 2003-06-28
Abstract
Abstract A programmable electronic computer is provided with a program storage having address locations for storing a program sequence, an address memory for storing an address of the program sequence to be executed, a program read out circuit connected to the address memory and program storage and adapted to read out a program step stored in an address location in the program storage addressed by the address memory. Circuitry is provided for determining, whether or not the contents of the program step read out by the read out circuit is an instruction. A controller is connected to the determination circuitry and is adapted to cause the program sequence stored in the program storage to be executed from the address stored in the address memory when the determination circuitry identifies the contents of the program step as an instruction, and to replace the address stored in the address memory with another address when the determination circuitry does not identify the contents of the program step as an instruction.
Inventors
- 👤 Harutsugu Aimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
227 words
A programmable computer comprising: a program memory for storing a plurality of program steps as an instruction of a program sequence, said program memory storing first information in a predetermined part of a first program step of said plurality of program steps and second information in a predetermined part of the remaining program steps of said plurality of program steps; address memory means for storing address information corresponding to at least one of said program steps; a first program step memory for storing a program step, corresponding to said address information stored in said address memory means, from said program memory; a second program step memory for storing a program step, corresponding to address information adjacent said address information stored in said address memory means, from said program memory; determination means connected to said first program step memory and to said second program step memory for determining the content in said predetermined parts of said program step stored in said first program step memory and of said program step stored in said second program step memory, said determination means producing a first signal when first information is stored at least in said first program step memory; and arithmetic operation means responsive to a first signal produced by said determination means for carrying out a program sequence from a program step stored in said first program step memory.
Claim 2
Dependent Claim
227 words
A programmable computer comprising: a program memory for storing a plurality of program steps as an instruction of a program sequence, said program memory storing first information in a predetermined part of a first program step of said plurality of program steps and second information in a predetermined part of the remaining program steps of said plurality of program steps; address memory means for storing address information corresponding to at least one of said program steps; a first program step memory for storing a program step, corresponding to said address information stored in said address memory means, from said program memory; a second program step memory for storing a program step, corresponding to address information adjacent said address information stored in said address memory means, from said program memory; determination means connected to said first program step memory and to said second program step memory for determining the content in said predetermined parts of said program step stored in said first program step memory and of said program step stored in said second program step memory, said determination means producing a first signal when first information is stored at least in said first program step memory; and arithmetic operation means responsive to a first signal produced by said determination means for carrying out a program sequence from a program step stored in said first program step memory.
Claim 3
Dependent Claim
50 words
A programmable computer according to claim 1, wherein said determination means produces a second signal when second information is stored in said first program step memory and said arithmetic operation means is responsive to said second signal and comprises means for updating said address information of said address memory means.
Claim 4
Dependent Claim
36 words
A programmable computer according to claim 1, wherein said address memory means comprises a first register for storing said address information and a second register for storing address information adjacent to said first mentioned address information.
Claim 5
Dependent Claim
15 words
A programmable computer according to claim 1, wherein said program memory is an addressable memory.
Claim 6
Dependent Claim
206 words
A programmable computer comprising: a program memory for storing a plurality of program steps as an instruction of a program sequence, said program memory storing first information in a predetermined part of a first program step of said plurality of program steps and second information in a predetermined part of the remaining program steps of said plurality of program steps; address memory means for storing address information corresponding to at least one of said plurality of program steps; a program step memory for storing a program step, corresponding to said address information stored in said address memory means, from said program memory; determination means connected to said program step memory for determining the content of said predetermined part of said program step stored in said program step memory, said determination means producing a first signal when first information is stored in said program step memory and producing a second signal when second information is stored in said program step memory; and arithmetic operation means responsive to a second signal produced by said determination means, when said determination means determines that second information is stored in said program memory, for initiating a program sequence from a program step different from that stored in said program step memory.
Claim 7
Dependent Claim
206 words
A programmable computer comprising: a program memory for storing a plurality of program steps as an instruction of a program sequence, said program memory storing first information in a predetermined part of a first program step of said plurality of program steps and second information in a predetermined part of the remaining program steps of said plurality of program steps; address memory means for storing address information corresponding to at least one of said plurality of program steps; a program step memory for storing a program step, corresponding to said address information stored in said address memory means, from said program memory; determination means connected to said program step memory for determining the content of said predetermined part of said program step stored in said program step memory, said determination means producing a first signal when first information is stored in said program step memory and producing a second signal when second information is stored in said program step memory; and arithmetic operation means responsive to a second signal produced by said determination means, when said determination means determines that second information is stored in said program memory, for initiating a program sequence from a program step different from that stored in said program step memory.
Claim 8
Dependent Claim
24 words
A programmable computer according to claim 5, wherein said arithmetic operation means comprises means for changing said address information in said address memory means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-13 | 1987-08-15 | 1988-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-13 | 1991-08-15 | 1992-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-13 | 1995-08-15 | 1996-02-14 | $7700.00 | Window Closed / Lapsed |