US4853845A
Expired / Lapsed
US
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Data processing apparatus for time-interleaved execution of a plurality of processes
Assignee: US Philips Corp
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Filing: 1986-08-27
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Granted: 1989-08-01
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Expires: 2006-08-27
Abstract
Abstract Because a customary data processing apparatus consisting of a program control section, an arithmetic and logic element and a data memory, also referred to as a microprocessor or microcontroller when integrated on a semiconductor chip, is temporarily not loaded by a control function in many applications, it is desirable to perform a plurality of such slow control functions by means of one apparatus. In order to achieve this as effectively as possible, in accordance with the invention there are added a sequencer and an address memory which is controlled by the sequencer and which takes up each time the next instruction address of a given control function or process which is each time associated with a sequence control signal. FOr the arithmetic and logic element there is preferably provided a buffer memory which is also controlled by the sequencer. As a result, several processes can be simply performed in a time-interleaved manner; a pipe-line structure can be formed by utilizing further intermediate memories so that the individual elements of the apparatus can be very effectively used.
Inventors
- 👤 Gunther A. H. Zimmer
- 👤 Dirk H. Braune
- 👤 Cecil H. Kaplinsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:53
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3888; G06F9/3836; G06F9/3851
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
543 words
An integrated circuit data processing apparatus for time-interleaved quasi-parallel execution of a plurality of processes, said apparatus comprising: a clock for generating a sequence of multi-pulse clock cycles, each cycle having a sequencer-controlling pulse; a sequencer under control of said sequencer-controlling clock pulse for recurrently stepping through a set of sequence control signals stored therein, each different sequence control signal corresponding to a different process; an instruction memory having a plurality of addressable locations for storing a set of instructions; an address memory for storing a plurality of instruction memory addresses for addressing said instruction memory locations, said address memory having an address input and a control input for receiving said sequence control signals, said address memory outputting an instruction memory address under control of a sequence control signal and a first address received on said address input; said instruction memory having an input for receiving an instruction memory address from said address memory and means for outputting an instruction stored in the addressed location; an instruction register receiving the output of said instruction memory for storing an instruction received from said instruction memory, and said instruction register having an output; an address generator receiving addresses from said address memory and having further condition/data inputs for generating said first address of a set of addresses stored therein for forwarding to said address input of said address memory a next following instruction memory address; an arithmetic and logic element having two data inputs and having a first control input for receiving control signals from said instruction register for under control of a current control signal executing a combining operation on two words received on said data inputs and a data output for outputting the result of said combining operation; a buffer memory having a data input for receiving the result from said data output of said arithmetic and logic element and for storing said result, said buffer memory having a data output for feeding a predetermined one of said two data inputs of said arithmetic and logic element, said buffer memory having a plurality of memory locations each addressable by a corresponding sequence control signal and having an address input for receiving said sequence control signals from said sequence under control of at least a part of said sequence control signal for accessing a corresponding memory location; a data memory having a plurality of addressable memory locations and an address input connected to the output of said instruction register responsive to part of an instruction from said instruction register for addressing a data memory location, a data input for receiving the result from said data output of said arithmetic and logic element and a data output for feeding the other one of said two data inputs of said arithmetic logic unit; a first dedicated connector for connecting said data memory to said instruction register and a second dedicated connector for connecting said buffer memory to said instruction register; a bidirectional connection circuit means having a control input for receiving sequence control signals from said sequencer, said connection circuit means being bidirectionally connected between said data memory and an external connection under control of a further part of said sequence control signal for controlling a data exchange between said data memory and the external connection.
Claim 2
Dependent Claim
543 words
An integrated circuit data processing apparatus for time-interleaved quasi-parallel execution of a plurality of processes, said apparatus comprising: a clock for generating a sequence of multi-pulse clock cycles, each cycle having a sequencer-controlling pulse; a sequencer under control of said sequencer-controlling clock pulse for recurrently stepping through a set of sequence control signals stored therein, each different sequence control signal corresponding to a different process; an instruction memory having a plurality of addressable locations for storing a set of instructions; an address memory for storing a plurality of instruction memory addresses for addressing said instruction memory locations, said address memory having an address input and a control input for receiving said sequence control signals, said address memory outputting an instruction memory address under control of a sequence control signal and a first address received on said address input; said instruction memory having an input for receiving an instruction memory address from said address memory and means for outputting an instruction stored in the addressed location; an instruction register receiving the output of said instruction memory for storing an instruction received from said instruction memory, and said instruction register having an output; an address generator receiving addresses from said address memory and having further condition/data inputs for generating said first address of a set of addresses stored therein for forwarding to said address input of said address memory a next following instruction memory address; an arithmetic and logic element having two data inputs and having a first control input for receiving control signals from said instruction register for under control of a current control signal executing a combining operation on two words received on said data inputs and a data output for outputting the result of said combining operation; a buffer memory having a data input for receiving the result from said data output of said arithmetic and logic element and for storing said result, said buffer memory having a data output for feeding a predetermined one of said two data inputs of said arithmetic and logic element, said buffer memory having a plurality of memory locations each addressable by a corresponding sequence control signal and having an address input for receiving said sequence control signals from said sequence under control of at least a part of said sequence control signal for accessing a corresponding memory location; a data memory having a plurality of addressable memory locations and an address input connected to the output of said instruction register responsive to part of an instruction from said instruction register for addressing a data memory location, a data input for receiving the result from said data output of said arithmetic and logic element and a data output for feeding the other one of said two data inputs of said arithmetic logic unit; a first dedicated connector for connecting said data memory to said instruction register and a second dedicated connector for connecting said buffer memory to said instruction register; a bidirectional connection circuit means having a control input for receiving sequence control signals from said sequencer, said connection circuit means being bidirectionally connected between said data memory and an external connection under control of a further part of said sequence control signal for controlling a data exchange between said data memory and the external connection.
Claim 3
Dependent Claim
34 words
An integrated circuit data processing apparatus as claimed in claim 1, wherein said connector circuit means comprises an output selector for selectively forwarding an instruction signal from said instruction register or external output signal.
Claim 4
Dependent Claim
77 words
A data processing apparatus as claimed in claim 1, further comprising: said arithmetic and logic element having a control output (carry, zero crossing, or change of sign); and a flag memory having a plurality of memory locations addressable by the sequence control signals, the number of different memory locations being determined by the number of different sequence control signals, and an output for supplying at least one condition signal to said data/condition input of said buffer register.
Claim 5
Dependent Claim
54 words
A data processing apparatus as claimed in claim 1, further comprising: a buffer register preceding said data inputs of the arithmetic and logic element and said data/condition signal input of the address generator, said buffer register storing any applied data immediately after the reading of either said data memory or of said buffer memory.
Claim 6
Dependent Claim
107 words
A data processing apparatus as claimed in claim 1, wherein said apparatus further comprises: a first read-only memory addressed in parallel by the content of said instruction address register, by data read from said data memory and by at least one condition signal; and a first switch controlled by an output of the instruction register, said first switch having a first position such that said buffer memory data input and said data memory data input are fed by the output of said first read-only memory and a second position such that said data memory and buffer memory data inputs are fed by said arithmetic and logic element.
Claim 7
Dependent Claim
34 words
An integrated circuit data processing apparatus as claimed in claim 1, wherein said connection circuit means comprises an input selector for selectively forwarding an external input signal or condition signal to said address generator.
Claim 8
Dependent Claim
119 words
A data processing apparatus as claimed in claim 6, wherein said input selector is a multiple multiplexer which is controlled by the sequence control signals and which derives at least some sequence control signals from condition signals on input lines of one of a plurality of groups of input lines feeding said multiplexer, each group of input lines being associated with a different sequence control signal, and said output selector for the instruction word being a multiple demultiplexer controlled by the sequence control signals and which connects at least some outputs of the instruction memory register to output lines of one of a plurality of groups of output lines, each group being associated with a different sequence control signal.
Claim 9
Dependent Claim
100 words
A data processing apparatus as claimed in claim 1, further comprising: a second read-only memory addressed in parallel by the content of the instruction address register and by a condition signal; and A second switch controlled by another output of the instruction register having a first position such that said predetermined one of said two data inputs of said arithmetic and logic element is fed by said data output of said data memory and a second position such that the other of said two data inputs of said arithmetic and logic element is fed by said buffer memory data output.
Claim 10
Dependent Claim
96 words
A data processing apparatus as claimed in claim 8, wherein the connection circuit means comprises a data connection circuit connected to the data memory for accessing said data memory only under control of control signals supplied from outside the apparatus , said data connection circuit comprising means for synchronizing said control signals with the clock signals of the clock generator and with sequence control signals; and said sequencer generating a predetermined sequence control signal for inhibiting the writing of data from the arithmetic and logic element or from the first read-only memory into the data memory.
Claim 11
Dependent Claim
56 words
A data processing apparatus as claimed in claim 9, wherein the synchronization circuits comprises a buffer memory for storing the data to be written which are applied to the connection circuit from the environment and the associated addresses for supply to the data memory under the control of the clock signals and the sequence control signals.
Claim 12
Dependent Claim
45 words
A data processing apparatus as claimed in claim 9, wherein the data memory is constructed as a dual-access memory having separate address inputs and separate data outputs, and two arbitrary addresses from which data can be read , in a time-independent manner for output on.
Claim 13
Dependent Claim
59 words
A data processing apparatus as claimed in claim 9, wherein for the quasi-simultaneous control of a plurality of input/output apparatus operations for a higher-order data processing system, the data processing system is connected to the data connection circuit the input/output apparatus being connected to further parts of the connection circuit means for the condition signals or the instruction word.
Claim 14
Dependent Claim
95 words
A data processing apparatus as claimed in claim 12, further comprising: a set of registers which comprises a plurality of control registers which correspond to the number of different sequence control signals, said control registers being accessible by the higher-order data processing system and each register being associated with another sequence control signal; and a logic circuit for generating an interrupt control signal for the higher-order data processing system when during a given sequence control signal the associated control register and at the same time a predetermined output of said instruction register carry predetermined values.
Claim 15
Dependent Claim
98 words
A data processing apparatus as claimed in claim 12, wherein said set of registers further comprises a plurality of stop registers corresponding to the number of different sequence control signals, said stop registers being accessible by the high-order data processing system and being associated with a respective sequence control signal; and a second logic circuit for generating a signal which inhibits the writing of data in said address storage memory, data memory, and buffer memory when the associated stop register and a predetermined output of the instruction register simultaneously carry predetermined values during a given sequence control signal.
Claim 16
Dependent Claim
446 words
An integrated circuit data processing apparatus as claimed in claim 1, further comprising: said clock having a plurality of clock outputs each for a respective clock pulse of said multi-pulse clock cycle; an instruction address register connected between said address memory and said address generator; said address memory having first and second control inputs for receiving sequence control signals; a sequence control register for storing a sequence control signal received from said sequencer having an output connected to said address memory, said buffer memory and said bidirectional connection circuit means; said sequencer having an output connected to said sequence control register and said first control input of said address memory; said sequencer being connected to a first clock output, and in response to a first clock pulse of a clock cycle received from said first clock output, said sequencer generating a sequence control signal corresponding to a next process, the memory location in the data memory addressed by the instruction register being read for supplying one of said data inputs of said arithmetic and logic element and said address generator, and the memory location of the buffer memory addressed by the output of the sequence control register being read for supplying the other of said data inputs of said arithmetic and logic element, said addressed locations of said buffer and data memories corresponding to a current process; in response to a second clock pulse, said arithmetic and logic element processing said supplied data associated with the current process for outputting the result on said arithmetic and logic element output, said address generator generating a next instruction address corresponding to a current process, and said address memory being addressed by said sequence control signal corresponding to said next process for reading a new address for the instruction memory; said address memory, buffer memory and data memory each having an input connected to a third clock output and upon receiving a third clock pulse said address memory storing said next instruction address for the current process at a memory location corresponding to the current process, said result on the output of said arithmetic and logic element being stored in the buffer memory at the location addressed by the sequence control signal stored in said sequence control register, and the instruction associated with said next process being read from said instruction memory; and said sequence control register, said instruction register and said instruction address register each having an input connected to a last clock output of said plurality of clock outputs for upon receiving a last clock pulse in a cycle storing, respectively, the sequence control signal, the instruction, and the instruction address each corresponding to said next process.
Claim 17
Dependent Claim
51 words
A data processing apparatus as claimed in claim 6, wherein the sequencer comprises a sequence counter whose capacity equals at least a predetermined maximum number of different sequence control signals, and a sequence control memory addressed by the sequence counter and which contains different sequence control signals in respective memory locations.
Claim 18
Dependent Claim
18 words
A data processing apparatus as claimed in claim 16, wherein the capacity of the sequence counter is adjustable.
Claim 19
Dependent Claim
92 words
A data processing apparatus as claimed in claim 16, wherein said sequence counter has a clock input connected to said second clock output and in response to a said second clock pulse said sequence counter generates a sequence control signal and said sequence control memory stores said sequence control signal; and said sequencer comprises a further sequence control register having a clock input connected to said first clock output for storing said sequence control signal from said sequence control memory upon receipt of a first clock pulse of said multi-pulse clock cycle.
Claim 20
Dependent Claim
17 words
A data processing apparatus as claimed in claim 16, wherein the sequence control memory is electrically modifiable.
Claim 21
Dependent Claim
112 words
A data processing apparatus as claimed in claim 19, wherein said apparatus further comprises: a first read-only memory which is addressed in parallel by the content of the said instruction address register, by data read from the said data memory and by at least one condition signal; and a first switch controlled by an output of said instruction register, said first switch having a first position such that said buffer memory data input and said data memory data input are fed the output data of said first read-only memory and a second position such that said data memory and buffer memory data inputs receive said result from said arithmetic and logic element.
Claim 22
Dependent Claim
103 words
A data processing apparatus as claimed in claim 20, wherein said apparatus further comprises: a second read-only memory addressed in parallel by the content of the instruction address register and by a said condition signal; and a second switch controlled by another output of the instruction register having a first position such that said predetermined one of said two data inputs of said arithmetic and logic unit receives said data output of said data memory and a second position such that the other of said two data inputs of said arithmetic and logic unit receives the output of said buffer memory data output.
Claim 23
Dependent Claim
54 words
A data processing apparatus as claimed in claim 21, further comprising a buffer register preceding said data inputs of said arithmetic and logic element and said data/condition signal input of said address generator, said buffer register storing any applied data immediately after the reading of either said data memory or of said buffer memory.
Claim 24
Dependent Claim
103 words
A data processing apparatus as claimed in claim 22, wherein said sequence counter has a clock input connected to said second clock output, and in response to a said second clock pulse said sequence counter generates a sequence control signal and said sequence control memory stores said sequence control signal; and said sequencer comprises a further sequence control register fed by said sequence control memory, said further sequence control register having a clock input connected to said first clock output for storing said sequence control signal from said sequence control memory upon receipt of a first clock pulse of said multi-pulse clock cycle.
Claim 25
Dependent Claim
96 words
A data processing apparatus as claimed in claim 23, wherein the connection circuit means comprises a data connection circuit connected to the data memory for accessing said data memory only under control of control signals supplied from outside the apparatus, said data connection circuit comprising synchronizing means for synchronizing said control signals with the clock signals of the clock generator and with sequence control signals and said sequencer generating a predetermined sequence control signal for inhibiting the writing of data from the arithmetic and logic element or from the first read-only memory into the data memory.
Claim 26
Dependent Claim
55 words
A data processing apparatus claimed in claim 24, wherein the synchronization means comprises a buffer memory for storing the data to be written which are applied to the connection circuit from the environment and the associated addresses for supply to the data memory under the control of the clock signals and the sequence control signals.
Claim 27
Dependent Claim
58 words
A data processing apparatus as claimed in claim 25, wherein said data memory is a dual-access memory comprising separate address inputs and separate data outputs, and two arbitrary addresses to which data can be applied via said separate address inputs and from which data can be read in a time-independent manner for output on said separate data outputs.
Claim 28
Dependent Claim
61 words
A data processing apparatus as claimed in claim 26, wherein for the quasi-simultaneous control of a plurality of input/output apparatus operations for a higher-order data processing system, the data processing system is connected to the data connection circuit and the input/output apparatus is connected to further parts of the connection circuit means for communicating the condition signals or the instruction word.
Claim 29
Dependent Claim
95 words
A data processing apparatus as claimed in claim 27, further comprising: a set of registers which comprises a plurality of control registers which correspond to the number of different sequence control signals, said control registers being accessible by the higher-order data processing system and each register being associated with another sequence control signal; and a logic circuit for generating an interrupt control signal for the higher-order data processing system when during a given sequence control signal the associated control register and at the same time a predetermined output of said instruction register carry predetermined values.
Claim 30
Dependent Claim
99 words
A data processing apparatus as claimed in claim 28, wherein said set of registers further comprises a plurality of stop registers corresponding to the number of different sequence control signals, said stop registers being accessible by the high-order data processing system and being associated with a respective sequence control signal; and a second logic circuit for generating a blocking signal which inhibits the writing of data in said address storage memory, data memory, and buffer memory when the associated stop register and a predetermined output of the instruction register simultaneously carry predetermined values during a given sequence control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-31 | 1993-01-30 | 1993-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-31 | 1997-01-30 | 1997-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-31 | 2001-01-30 | 2001-08-01 | $7700.00 | Window Closed / Lapsed |