Voltage threshold detection circuit with very low power consumption

Claim 2

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and connected to provide an output at an output node in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising: first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on an active phase of said first clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on an active phase of said second clock signal; and a third clocked switch connected to connect said second capacitor to said input node of said voltage detection circuit on an active phase of said first clock signal; and logic circuitry, powered from said power-supply voltage, and connected to receive the output of said voltage-detection circuitry, and connected to provide an alarm signal when said output of said voltage-detection circuitry enters said first state.

Claim 3

The integrated circuit of claim 1, wherein both said clock signals are received both in true and in complemented forms, and each said switch consists of a parallel combination of an N-channel transistor with a P-channel transistor.

Claim 4

The integrated circuit of claim 1, wherein said voltage-detection circuit comprises a transistor, clocked by said second clock signal, which forces the output of said voltage detection circuit out of said first state during an active phase of said second clock signal.

Claim 5

The integrated circuit of claim 1, wherein said voltage detection circuit comprises a field-effect transistor having a gate connected to said input node.

Claim 6

The integrated circuit of claim 1, wherein said voltage-detection circuit provides said output in said first state when the voltage at said input node rises above said predetermined limit voltage.

Claim 7

The integrated circuit of claim 1, wherein said logic circuitry includes latching circuitry connected to hold an output of said logic circuitry in a no-alarm condition, but not to hold said output of said logic circuitry in an alarm condition.

Claim 8

The integrated circuit of claim 1, wherein both said first and second clock signals have duty cycles of less than 30%.

Claim 9

The integrated circuit of claim 1, wherein said first and second clock signals are non-overlapping.

Claim 10

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and Connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising: at least one capacitance; clocked transfer switches connected to transfer a voltage from said power-supply voltage connection onto said capacitance, and to transfer a voltage from said capacitance onto said input node on an active phase of said first clock signal; and a clocked precharge switch connected to fix the voltage of said output of said voltage-detection circuit on an active phase of said second clock signal; and logic circuitry, powered from said power-supply voltage, and connected to receive the output of said voltage-detection circuitry, and connected to provide an alarm signal when said output of said voltage-detection circuitry enters said first state.

Claim 11

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and Connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising: at least one capacitance; clocked transfer switches connected to transfer a voltage from said power-supply voltage connection onto said capacitance, and to transfer a voltage from said capacitance onto said input node on an active phase of said first clock signal; and a clocked precharge switch connected to fix the voltage of said output of said voltage-detection circuit on an active phase of said second clock signal; and logic circuitry, powered from said power-supply voltage, and connected to receive the output of said voltage-detection circuitry, and connected to provide an alarm signal when said output of said voltage-detection circuitry enters said first state.

Claim 12

The integrated circuit of claim 9, wherein both said clock signals are received both in true and in complemented forms, and each said switch consists of a parallel combination of an N-channel transistor with a P-channel transistor.

Claim 13

The integrated circuit of claim 9, wherein said voltage-detection circuit comprises a transistor, clocked by said second clock signal, which forces the output of said voltage-detection circuit out of said first state during an active phase of said second clock signal.

Claim 14

The integrated circuit of claim 9, wherein said voltage-detection circuit comprises a field-effect transistor having a gate connected to said input node.

Claim 15

The integrated circuit of claim 9, wherein said voltage-detection circuit provides said output in said first state if the voltage at said input node rises above said predetermined limit voltage.

Claim 16

The integrated circuit of claim 9, wherein said logic circuitry includes latching circuitry connected to hold an output of said logic circuitry in a no-alarm condition, but not to hold said output of said logic circuitry in an alarm condition.

Claim 17

The integrated circuit of claim 9, wherein said first and second clock signals are non-overlapping.

Claim 18

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising: first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on an active phase of said first clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on an active phase of said second clock signal; and a third clocked switch connected to connect said second capacitor to said input node of said voltage detection circuit on an active phase of said first clock signal; and logic circuitry, powered from said power-supply voltage connected to receive the output of said voltage-detection circuitry, and connected to provide an alarm signal when said output of said voltage-detection circuitry enters said first state; a load element connected to pull said input node away from said limit voltage, and thereby prevent said output of said voltage-detection circuitry from entering said first state, at least during an active phase of said second clock signal.

Claim 19

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising: first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on an active phase of said first clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on an active phase of said second clock signal; and a third clocked switch connected to connect said second capacitor to said input node of said voltage detection circuit on an active phase of said first clock signal; and logic circuitry, powered from said power-supply voltage connected to receive the output of said voltage-detection circuitry, and connected to provide an alarm signal when said output of said voltage-detection circuitry enters said first state; a load element connected to pull said input node away from said limit voltage, and thereby prevent said output of said voltage-detection circuitry from entering said first state, at least during an active phase of said second clock signal.

Claim 20

The integrated circuit of claim 16, wherein both said clock signals are received both in true and in complemented forms, and each said switch consists of a parallel combination of an N-channel transistor with a P-channel transistor.

Claim 21

The integrated circuit of claim 16, wherein said voltage-detection circuit comprises a transistor, clocked by said second clock signal, which forces the output of said voltage-detection circuit out of said first state during an active phase of said second clock signal.

Claim 22

The integrated circuit of claim 16, wherein said voltage-detection circuit comprises a field-effect transistor having a gate connected to said input node.

Claim 23

The integrated circuit of claim 16, wherein said voltage-detection circuit provides said output in said first state when the voltage at said input node rises above said predetermined limit voltage.

Claim 24

The integrated circuit of claim 16, wherein said logic circuitry includes latching circuitry connected to hold an output of said logic circuitry in a no-alarm condition, but not to hold said output of said logic circuitry in an alarm condition.

Claim 25

The integrated circuit of claim 16, wherein said load element is not clocked.

Claim 26

The integrated circuit of claim 16, wherein said load element consists of a resistor.

Claim 27

The integrated circuit of claim 16, wherein both said first and second clock signals have duty cycles of less than 30%.

Claim 28

The integrated circuit of claim 16, wherein said first and second clock signals are non-overlapping.

Claim 29

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply the input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, said two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during said first phase, and latch circuitry powered from said input voltage, and connected to latch the logic level of the drain of said detection transistor; wherein said detection transistor is powered from said input voltage and is connected to be powered during some, but not all, portions of said first and second phases.

Claim 30

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply the input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, said two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during said first phase, and latch circuitry powered from said input voltage, and connected to latch the logic level of the drain of said detection transistor; wherein said detection transistor is powered from said input voltage and is connected to be powered during some, but not all, portions of said first and second phases.

Claim 31

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply said input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, said two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during said first phase, and latch circuitry connoted to latch a logic level of the drain of said detection transistor; wherein said detection transistor is connected to be powered during some, but not all, portions of said first and second phases; wherein the latching circuit comprises an inverter having its input connected to the drain of the detection transistor, its output constituting an output of the circuit to detect the crossing of a voltage level, and a feedback transistor controlled by the output of said inverter and connected to the drain of said detection transistor.

Claim 32

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply said input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, said two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during said first phase, and latch circuitry connoted to latch a logic level of the drain of said detection transistor; wherein said detection transistor is connected to be powered during some, but not all, portions of said first and second phases; wherein the latching circuit comprises an inverter having its input connected to the drain of the detection transistor, its output constituting an output of the circuit to detect the crossing of a voltage level, and a feedback transistor controlled by the output of said inverter and connected to the drain of said detection transistor.

Claim 33

A circuit according to claim 27, wherein said feedback transistor is a P channel transistor having its source connected to a supply voltage and its drain connected to the drain of said detection transistor.

Claim 34

A circuit according to claim 27, comprising an asymmetrical clock giving peaks of different durations for said first phase and said second phase.

Claim 35

A circuit according to claim 29, wherein said clock gives peaks that are shorter for said first phase than for said second phase.

Claim 36

A circuit according to claim 29, wherein the periodic peaks given by said clock for said first phase do not have any overlapping with the periodic peaks given for said second phase.

Claim 37

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply said input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, the two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during the first phase, and latch circuitry powered from said input voltage, and connected to latch the logic level of the drain of the detection transistor; wherein said detection transistor is powered from said input voltage and is connected to be powered during some, but not all, portions of said first and second phases; wherein said input voltage is connected to a voltage supply terminal of said circuit.

Claim 38

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply said input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, the two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during the first phase, and latch circuitry powered from said input voltage, and connected to latch the logic level of the drain of the detection transistor; wherein said detection transistor is powered from said input voltage and is connected to be powered during some, but not all, portions of said first and second phases; wherein said input voltage is connected to a voltage supply terminal of said circuit.

Claim 39

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply said input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, said two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during said first phase, and latch circuitry powered from said input voltage, and connected to latch the logic level of the drain of said detection transistor; wherein said detection transistor is connected to be powered during some, but not all, portions of said first and second phases; said circuit being incorporated into an integrated circuit chip and comprising an output capable of inhibiting the operation of said other circuits placed on the same chip, in the event of the overrunning of a voltage threshold at said input of said detection circuit or of the detection of a bottom threshold.

Claim 40

A circuit for the detection of the overrunning of the level of an input voltage, said circuit comprising: at least one first capacitor and one second capacitor and a set of switches actuated successively and interconnected with said capacitors and a detection transistor so that: in a first phase, said switches apply said input voltage to the terminals of said first capacitor and apply the voltage present at the terminals of said second capacitor to the gate of said detection transistor, said two capacitors being isolated from each other; and in a second phase, said switches connect said two capacitors so that said second capacitor is charged by said first capacitor, said capacitors being insulated from the input and from the gate of said detection transistor; means for precharging the drain of said detection transistor during said second phase, means for discharging said second capacitor during said first phase, and latch circuitry powered from said input voltage, and connected to latch the logic level of the drain of said detection transistor; wherein said detection transistor is connected to be powered during some, but not all, portions of said first and second phases; said circuit being incorporated into an integrated circuit chip and comprising an output capable of inhibiting the operation of said other circuits placed on the same chip, in the event of the overrunning of a voltage threshold at said input of said detection circuit or of the detection of a bottom threshold.

Claim 43

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals having different respective active phases; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising; first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on an active phase of said first clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on an active phase of said second clock signal; and a third clocked switch connected to connect said second capacitor to said voltage detection circuit on an active phase of said first clock signal; clocked precharge switches connected to intermittently precharge said output node of said voltage-detection circuit, during an active phase of said second clock signal, away from said first state; and latching circuitry powered from said power-supply voltage, and connected to hold said output of said voltage-detection circuit out of said first state, but not to hold said output of said voltage-detection circuit in said first state.

Claim 44

An integrated circuit, comprising: a connection for receiving a power-supply voltage; connections for receiving first and second clock signals having different respective active phases; a voltage-detection circuit, powered from said power-supply voltage, having an input node, and connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising; first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on an active phase of said first clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on an active phase of said second clock signal; and a third clocked switch connected to connect said second capacitor to said voltage detection circuit on an active phase of said first clock signal; clocked precharge switches connected to intermittently precharge said output node of said voltage-detection circuit, during an active phase of said second clock signal, away from said first state; and latching circuitry powered from said power-supply voltage, and connected to hold said output of said voltage-detection circuit out of said first state, but not to hold said output of said voltage-detection circuit in said first state.

Claim 45

The integrated circuit of claim 35, wherein both said clock signals are received both in true and in complemented forms, and each said switch consists of a parallel combination of an N-channel transistor with a P-channel transistor.

Claim 46

The integrated circuit of claim 35, further comprising an unclocked load element connected to said input node of said voltage-detection circuit.

Claim 47

The integrated circuit of claim 35, wherein said voltage detection circuit comprises a transistor, clocked by said second clock signal, which forces the output of said voltage-detection circuit out of said first state during an active phase of said second clock signal.

Claim 48

The integrated circuit of claim 35, wherein said voltage-detection circuit comprises a field-effect transistor having a gate connected to said input node.

Claim 49

The integrated circuit of claim 35, wherein said voltage detection circuit provides said output in said first state if the voltage at said input node rises above predetermined limit voltage.

Claim 50

The integrated circuit of claim 35, wherein both said first and second clock signals have duty cycles of less than 30%.

Claim 51

The integrated circuit of claim 35, wherein said first and second clock signals have non-overlapping active phases.

Claim 52

The integrated circuit of claim 35, incorporated into an integrated circuit chip which also comprises other circuits, and comprising an output connected to inhibit the operation of the other circuits placed on the same chip, in the event of the overrunning of a voltage threshold at the input of the detection circuit or of the detection of a bottom threshold.

Claim 53

An integrated circuit, comprising: a connection for receiving an input voltage; connections for receiving multiple different clock signals; a voltage-detection circuit, powered from said input voltage, having an input node, and connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising; first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on a first active phase of said clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on a second active phase of said clock signals which does not overlap with said first active phase; and a third clocked switch connected to connect said second capacitor to said voltage detection circuit on an active phase of said clock signals which is different from said second active phase; a clocked precharge switch connected to intermittently precharge said output node of said voltage-detection circuit, on an active phase of said clock signals which is different from said second active phase; and latching circuitry powered from said input voltage, and connected to hold said output of said voltage-detection circuit out of said first state, but not to hold said output of said voltage-detection circuit in said first state.

Claim 54

An integrated circuit, comprising: a connection for receiving an input voltage; connections for receiving multiple different clock signals; a voltage-detection circuit, powered from said input voltage, having an input node, and connected to provide an output in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said power-supply voltage connection and said voltage-detection circuit, and comprising; first and second capacitors, having respective capacitances in a predetermined ratio; a first clocked switch connected to transfer said power-supply voltage onto said first capacitor, on a first active phase of said clock signal; and a second clocked switch connected to connect said first and second capacitors, to effect charge sharing therebetween, on a second active phase of said clock signals which does not overlap with said first active phase; and a third clocked switch connected to connect said second capacitor to said voltage detection circuit on an active phase of said clock signals which is different from said second active phase; a clocked precharge switch connected to intermittently precharge said output node of said voltage-detection circuit, on an active phase of said clock signals which is different from said second active phase; and latching circuitry powered from said input voltage, and connected to hold said output of said voltage-detection circuit out of said first state, but not to hold said output of said voltage-detection circuit in said first state.

Claim 55

The integrated circuit of claim 44, wherein all said clock signals are received both in true and in complemented forms, and each said switch consists of a parallel combination of an N-channel transistor with a P-channel transistor.

Claim 56

The integrated circuit of claim 44, wherein said voltage detection circuit comprises a transistor, clocked by said second clock signal, which forces the output of said voltage-detection circuit out of said first state during an active phase of said second clock signal.

Claim 57

The integrated circuit of claim 44, wherein said voltage detection circuit comprises a field-effect transistor having a gate connected to said input node.

Claim 58

The integrated circuit of claim 44, further comprising an unclocked load element connected to said input node of said voltage-detection circuit.

Claim 59

The integrated circuit of claim 44, wherein said voltage-detection circuit provides said output in said first state when the voltage at said input node rises above said predetermined limit voltage.

Claim 60

The integrated circuit of claim 44, wherein said clock signals are non-overlapping.

Claim 61

The integrated circuit of claim 44, wherein all said clock signals have duty cycles of less than 30%.

Claim 62

The integrated circuit of claim 44, incorporated into an integrated circuit chip which also comprises other circuits, and comprising an output connected to inhibit the operation of said other circuits placed on the same chip, in the event of the overrunning of said voltage threshold at said input node of said voltage-detection circuit or of the detection of a bottom threshold.

Claim 63

An integrated circuit, comprising: a connection for receiving an input voltage; connections for receiving multiple non-overlapping clock signals; a voltage-detection circuit, powered from said input voltage, having an input node, and connected to provide an output at an output node in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said input voltage connection and said voltage-detection circuit, and comprising one or more capacitors interconnected with clocked transfer switches which are connected to intermittently transfer a voltage from said input voltage connection onto said capacitors, and to intermittently transfer a voltage from said capacitors to said input node of said voltage detection circuit, in dependence on the timing of said clock signals; a clocked precharge switch connected to intermittently precharge said output node of said voltage-detection circuit, during at least some times when voltage is not being transferred from said capacitors to said input node, away from said first state; and latching circuitry powered from said input voltage, and connected to hold said output of said voltage-detection circuit out of said first state.

Claim 64

An integrated circuit, comprising: a connection for receiving an input voltage; connections for receiving multiple non-overlapping clock signals; a voltage-detection circuit, powered from said input voltage, having an input node, and connected to provide an output at an output node in a first state when and only when the voltage of said input node passes a predetermined limit voltage; and a charge-transfer circuit, interposed between said input voltage connection and said voltage-detection circuit, and comprising one or more capacitors interconnected with clocked transfer switches which are connected to intermittently transfer a voltage from said input voltage connection onto said capacitors, and to intermittently transfer a voltage from said capacitors to said input node of said voltage detection circuit, in dependence on the timing of said clock signals; a clocked precharge switch connected to intermittently precharge said output node of said voltage-detection circuit, during at least some times when voltage is not being transferred from said capacitors to said input node, away from said first state; and latching circuitry powered from said input voltage, and connected to hold said output of said voltage-detection circuit out of said first state.

Claim 65

The integrated circuit of claim 53, wherein all said clock signals are received both in true and in complemented forms, and each said switch consists of a parallel combination of an N-channel transistor with a P-channel transistor.

Claim 66

The integrated circuit of claim 53, wherein said voltage detection circuit comprises a transistor, clocked by said second clock signal, which forces the output of said voltage detection circuit out of said first state during an active phase of said second clock signal.

Claim 67

The integrated circuit of claim 53, wherein said voltage detection circuit comprises a field-effect transistor having a gate connected to said input node.

Claim 68

The integrated circuit of claim 53, wherein said voltage detection circuit provides said output in said first state if the voltage at said input node rises above predetermined limit voltage.

Claim 69

The integrated circuit of claim 53, further comprising an unclocked load element connected to said input node of said voltage-detection circuit.

Claim 70

The integrated circuit of claim 53, wherein all said clock signals have duty cycles of less than 30%.

Claim 71

The integrated circuit of claim 53, incorporated into an integrated circuit chip which also comprises other circuits, and comprising an output connected to inhibit the operation of the other circuits placed on the same chip, in the event of the overrunning of a voltage threshold at the input of the detection circuit or of the detection of a bottom threshold.