Patent US5438665A successfully refreshed from Google Patents.
US5438665A
Expired / Lapsed
US
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Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer control information
Assignee: Fujitsu Ltd
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Filing: 1994-02-01
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Granted: 1995-08-01
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Expires: 2014-02-01
Abstract
Abstract A direct memory access controller coupled to a system bus of a system for controlling data transfers through a channel includes the following. A request handler receives a transfer request generated by a device connected to the system bus. A transfer control information register stores transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from the request handler. A temporary register stores the transfer control information necessary for processing the next transfer request. A transfer control information setting circuit generates the transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in the transfer control information register during the data transfer by the present transfer request and then renewing the transfer control information and-temporary registers with the generated transfer control information. A transfer execution circuit executes the actual data transfer through the system bus in accordance with the transfer control information registered in the temporary register, which is output to the system bus therefrom.
Inventors
- 👤 Takayoshi Taniai
- 👤 Yasuhiro Tanaka
- 👤 Tadashi Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:26
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
307 words
A direct memory access controller for controlling data transfers, during sequential transfer cycles which include a current transfer cycle and a subsequent transfer cycle, through a system bus via a plurality of channels, said direct memory access controller comprising: request handling means connected to receive signals carried on the system bus, for receiving a transfer data request generated by a device connected to said system bus and for outputting transfer control information; first register means connected to receive the transfer control information from said request handling means, for storing the transfer control information; second register means connected to receive the transfer control information from said first register means, for storing the transfer control information; said first register means and said second register means respectively include transfer control information concerning the plurality of channels; transfer execution means, operatively connected to said second register means, for executing the data transfer during the current transfer cycle in accordance with the transfer control information read out from said second register means; said transfer execution means being connected to receive the transfer data request from said request handling means, and said transfer execution means being responsive to the transfer data request; and transfer control information generation means, operatively connected to said first and second register means, for reading out transfer control information from said first register means during the current transfer cycle and for generating an updated transfer control information, said updated transfer control information being used during the subsequent transfer cycle, by updating the transfer control information read out from said first register means during the current transfer cycle, said transfer control information generating means sequentially writing the updated transfer control information into said second register means after the transfer control information stored in the second register means is read out by said transfer execution means during the current transfer cycle.
Claim 2
Dependent Claim
307 words
A direct memory access controller for controlling data transfers, during sequential transfer cycles which include a current transfer cycle and a subsequent transfer cycle, through a system bus via a plurality of channels, said direct memory access controller comprising: request handling means connected to receive signals carried on the system bus, for receiving a transfer data request generated by a device connected to said system bus and for outputting transfer control information; first register means connected to receive the transfer control information from said request handling means, for storing the transfer control information; second register means connected to receive the transfer control information from said first register means, for storing the transfer control information; said first register means and said second register means respectively include transfer control information concerning the plurality of channels; transfer execution means, operatively connected to said second register means, for executing the data transfer during the current transfer cycle in accordance with the transfer control information read out from said second register means; said transfer execution means being connected to receive the transfer data request from said request handling means, and said transfer execution means being responsive to the transfer data request; and transfer control information generation means, operatively connected to said first and second register means, for reading out transfer control information from said first register means during the current transfer cycle and for generating an updated transfer control information, said updated transfer control information being used during the subsequent transfer cycle, by updating the transfer control information read out from said first register means during the current transfer cycle, said transfer control information generating means sequentially writing the updated transfer control information into said second register means after the transfer control information stored in the second register means is read out by said transfer execution means during the current transfer cycle.
Claim 3
Dependent Claim
34 words
The direct memory access controller as claimed in claim 1, wherein each of said first and second register means comprises register portions respectively assigned to said plurality of channels provided for the data transfer.
Claim 4
Dependent Claim
45 words
The A direct memory access controller as claimed in claim 1, wherein said transfer control information generation means starts to generate the updated transfer control information necessary for executing the data transfer by a next transfer data request when a present transfer data request occurs.
Claim 5
Dependent Claim
84 words
The direct memory access controller as claimed in claim 1, wherein said first register means comprises a first register which registers control information necessary for controlling the data transfer, a second register which registers a byte count indicative of an amount of data to be transferred, and a third register which registers address information relating to the data transfer, and wherein said control information, said byte count and said address information form said transfer control information to be registered in the first register means.
Claim 6
Dependent Claim
74 words
The direct memory access controller as claimed in claim 1, wherein said second register means comprises a first register which registers control information necessary for controlling the data transfer by a next transfer request, and a second register for registering address information relating to the data transfer by said next transfer request, and wherein said control information and said address information form the transfer control information to be registered in said second register means.
Claim 7
Dependent Claim
25 words
The direct memory access controller as claimed in claim 1, further comprising an internal bus to which said first and second register means are coupled.
Claim 8
Dependent Claim
21 words
The direct memory access controller as claimed in claim 1, wherein said second register means is coupled to said system bus.
Claim 9
Dependent Claim
93 words
The direct memory access controller as claimed in claim 1, wherein said transfer control information generation means comprises a programmable logic array means for controlling a sequence of the data transfer executed by said transfer execution means and for controlling a sequence of generating said updated transfer control information from the transfer control information from said first register means, a microsequencer means for controlling said programmable logic array, and an arithmetic and logic unit means for generating said updated transfer control information necessary for executing the data transfer by the subsequent transfer cycle.
Claim 10
Dependent Claim
52 words
The direct memory access controller as claimed in claim 8, wherein the transfer control information includes control information necessary for controlling the data transfer, a byte count indicative of an amount of data to be transferred, and address information including a source address and a destination address relating to the data transfer.
Claim 11
Dependent Claim
42 words
The direct memory access controller as claimed in claim 6, wherein said arithmetic and logic unit comprises a first arithmetic and logic unit for generating source addresses and destination addresses, and a second arithmetic and logic unit for generating a byte count.
Claim 12
Dependent Claim
45 words
The direct memory access controller as claimed in claim 6, wherein said transfer execution means comprises a data temporary register for temporarily storing data to be transferred, and a data swapper means for exchanging of data between said system bus and said data temporary register.
Claim 13
Dependent Claim
277 words
A direct memory access controller for controlling data transfers during sequential transfer cycles which include a current transfer cycle and a subsequent transfer cycle, through a system bus via a plurality of channels, said direct memory access controller comprising: an internal bus; a control circuit generating a plurality of transfer control data; a first register circuit operatively connected to the internal bus to receive said plurality of transfer control data, said first register circuit storing said plurality of transfer control data; a second register circuit operatively connected to the internal bus to receive said plurality of transfer control data, said second register circuit storing plurality of transfer control data; said first register circuit and said second register circuit respectively include transfer control data concerning the plurality of channels; a transfer execution circuit, operatively connected to the second register circuit, for carrying out data transfer via the internal bus during the current transfer cycle in accordance with the plurality of transfer control data read out from said second register circuit; and said control circuit being operatively connected to the first and second register circuits and generating said plurality of transfer control data, said plurality of transfer control data being used during a subsequent transfer cycle, by updating said plurality of transfer control data read out from said first register circuit during the current transfer cycle to form a plurality of updated transfer control data and sequentially writing said plurality of updated transfer control data into said second register circuit via the internal bus after said plurality of transfer control data is read out from said second register circuit by said transfer execution circuit during the current transfer cycle.
Claim 14
Dependent Claim
277 words
A direct memory access controller for controlling data transfers during sequential transfer cycles which include a current transfer cycle and a subsequent transfer cycle, through a system bus via a plurality of channels, said direct memory access controller comprising: an internal bus; a control circuit generating a plurality of transfer control data; a first register circuit operatively connected to the internal bus to receive said plurality of transfer control data, said first register circuit storing said plurality of transfer control data; a second register circuit operatively connected to the internal bus to receive said plurality of transfer control data, said second register circuit storing plurality of transfer control data; said first register circuit and said second register circuit respectively include transfer control data concerning the plurality of channels; a transfer execution circuit, operatively connected to the second register circuit, for carrying out data transfer via the internal bus during the current transfer cycle in accordance with the plurality of transfer control data read out from said second register circuit; and said control circuit being operatively connected to the first and second register circuits and generating said plurality of transfer control data, said plurality of transfer control data being used during a subsequent transfer cycle, by updating said plurality of transfer control data read out from said first register circuit during the current transfer cycle to form a plurality of updated transfer control data and sequentially writing said plurality of updated transfer control data into said second register circuit via the internal bus after said plurality of transfer control data is read out from said second register circuit by said transfer execution circuit during the current transfer cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-31 | 1999-01-30 | 1999-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-31 | 2003-01-30 | 2003-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-31 | 2007-01-30 | 2007-08-01 | $7700.00 | Window Closed / Lapsed |