US5018098A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transfer controlling apparatus for direct memory access
Assignee: Fujitsu Ltd
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Filing: 1988-04-27
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Granted: 1991-05-21
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Expires: 2008-04-27
Abstract
Abstract A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers, each of which registers stores microaddress information for program processing of the data transfer for a corresponding channel; a second microaddress register which stores microaddress information for program processing other than the program processing of the data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with microaddress information read out from a selected one of the first microaddress registers and the second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of the microaddress information read out from the selected one of the first microaddress registers and the second microaddress register, and for writing the incremented microaddress information to the selected one of the first microaddress registers and the second microaddress register; the microaddress information stored in one of the first microaddress registers for the corresponding channel being read out when program processing of data transfer for the corresponding channel is carried out, the microaddress information stored in the second microaddress register being read out when program processing other than the program processing of data transfer is carried out.
Inventors
- 👤 Takayoshi Taniai
- 👤 Tadashi Saitoh
- 👤 Atsushi Fujihira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:40
CPC Classifications
B; B08; B08B; B08B1/00; G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/285
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
241 words
A data transfer controlling apparatus for direct memory access comprising: at least one first microaddress register, each register storing first microaddress information, said first microaddress information being for program processing of data transfer for a corresponding channel; a second microaddress register which stores second microaddress information, said second microaddress information being for operational program processing other than said program processing of said data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with said first and second microaddress information respectively read out from a selected one of said first microaddress registers and said second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of said first and second microaddress information respectively read out from the selected one of said first microaddress registers and said second microaddress register, and for respectively writing said incremented first and second microaddress information to said selected one of said first microaddress registers and said second microaddress register, said first microaddress information stored in one of said first microaddress registers for said corresponding channel being read out when said program processing of said data transfer for said corresponding channel is carried out, said second microaddress information stored in said second microaddress register being read out when operational program processing other than said program processing of said data transfer is carried out.
Claim 2
Dependent Claim
241 words
A data transfer controlling apparatus for direct memory access comprising: at least one first microaddress register, each register storing first microaddress information, said first microaddress information being for program processing of data transfer for a corresponding channel; a second microaddress register which stores second microaddress information, said second microaddress information being for operational program processing other than said program processing of said data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with said first and second microaddress information respectively read out from a selected one of said first microaddress registers and said second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of said first and second microaddress information respectively read out from the selected one of said first microaddress registers and said second microaddress register, and for respectively writing said incremented first and second microaddress information to said selected one of said first microaddress registers and said second microaddress register, said first microaddress information stored in one of said first microaddress registers for said corresponding channel being read out when said program processing of said data transfer for said corresponding channel is carried out, said second microaddress information stored in said second microaddress register being read out when operational program processing other than said program processing of said data transfer is carried out.
Claim 3
Dependent Claim
90 words
A data transfer controlling apparatus according to claim 1, further comprising a microaddress register control unit, said control unit supplying a read signal and write signal for said microaddress information to one of said first microaddress registers for said corresponding channel when said program processing of the data transfer for said corresponding channel is carried out, said control unit supplying a read signal and write signal for said microaddress information to said second microaddress register when program processing other than said program processing of the data transfer is carried out.
Claim 4
Dependent Claim
49 words
A data transfer controlling apparatus according to claim 2, wherein said control unit comprises means for receiving a bus error signal and supplies said read signal and said write signal for said microaddress information to said second microaddress register when program processing for bus error processing is carried out.
Claim 5
Dependent Claim
69 words
A data transfer controlling apparatus according to claim 2, wherein said control unit comprises means for receiving a channel indication signal and a transfer request signal for said program processing of the data transfer and receives said transfer request signal for a channel newly indicated by said channel indication signal before said program processing of data transfer for another channel previously indicated by said channel indication signal is completed.
Claim 6
Dependent Claim
52 words
A data transfer controlling apparatus according to claim 1, further comprising a mapping programmable logic array, the microaddress information read out from said mapping programmable logic array being written to said first microaddress registers while program processing based on the microaddress information read out from said second microaddress register is carried out.
Claim 7
Dependent Claim
41 words
A data transfer controlling apparatus according to claim 5, wherein said microaddress information read out from said mapping programmable logic array is written to said first microaddress registers in accordance with a write instruction supplied from said micro read only memory.
Claim 8
Dependent Claim
33 words
A data transfer controlling apparatus according to claim 5, wherein said microaddress information read out from said mapping programmable logic array is initial microaddress information to be stored in said first microaddress registers.
Claim 9
Dependent Claim
46 words
A data transfer controlling apparatus according to claim 5, wherein said microaddress information read out from said mapping programmable logic array is written to said first microaddress registers at start processing which is carried out before said program processing of the data transfer is carried out.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |