Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
211 words
A microcomputer having an arithmetic logic unit for sequentially executing the processing of instructions read out successively from a main memory, a first group of registers for storing data to be processed by the arithmetic logic unit and data as a result of the processing operation thereof, a buffer register used for buffering the data communication between the microcomputer and external resources including the main memory, and an internal bus line through which the arithmetic logic unit, the first group of registers and the buffer register are communicated with one another, characterized in that a second group (20) of registers prepared for use in the processing of required auxiliary functions are connected with said internal bus line (10, 12, 14) and that a microprogram storage and control means (30) is provided which stores microinstructions both for the instruction processing and for the processing of the required auxiliary functions and controls the arithmetic logic unit (16), the first and the second groups (18,20) of registers and the buffer register (22), whereby the arithmetic logic unit, the buffer register and the internal bus line are shared by the instruction processing and the processing of the required auxiliary functions by executing the microinstructions read out from the microprogram storage and control means (30) successively.
Claim 2
Dependent Claim
211 words
A microcomputer having an arithmetic logic unit for sequentially executing the processing of instructions read out successively from a main memory, a first group of registers for storing data to be processed by the arithmetic logic unit and data as a result of the processing operation thereof, a buffer register used for buffering the data communication between the microcomputer and external resources including the main memory, and an internal bus line through which the arithmetic logic unit, the first group of registers and the buffer register are communicated with one another, characterized in that a second group (20) of registers prepared for use in the processing of required auxiliary functions are connected with said internal bus line (10, 12, 14) and that a microprogram storage and control means (30) is provided which stores microinstructions both for the instruction processing and for the processing of the required auxiliary functions and controls the arithmetic logic unit (16), the first and the second groups (18,20) of registers and the buffer register (22), whereby the arithmetic logic unit, the buffer register and the internal bus line are shared by the instruction processing and the processing of the required auxiliary functions by executing the microinstructions read out from the microprogram storage and control means (30) successively.
Claim 3
Dependent Claim
39 words
A microcomputer as defined in claim 1, wherein said auxiliary function is a direct memory access control and said second group of registers is used for storing a source address and a destination address of data to be transferred.
Claim 4
Dependent Claim
34 words
A microcomputer as defined in claim 1, wherein said auxiliary function is a dynamic memory refresh control and said second group of registers is used for storing the address of data to be refreshed.
Claim 5
Dependent Claim
64 words
A microcomputer as defined in claim 1, wherein addresses as a part of the address space of the main memory are allocated to said second group of registers, whereby said second group (20) of registers functions as a stack for temporarily saving the content of said first group of registers when the interrupt of the then executed processing is requested from the external resources.
Claim 6
Dependent Claim
39 words
A microcomputer as defined in one of claims 1 to 4, wherejnboth said first and said second groups (18, 20) of registers are allocated on a single random access memory, to which addresses of each register group are assigned.