Transistor arrangement for forming basic cell of master-slice type semiconductor integrated circuit device and master-slice type semiconductor integrated circuit device

Claim 2

A master-slice type semiconductor integrated circuit device comprising: a first transistor; and a second transistor; the first and second transistors being arranged side by side in a first direction; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first gate electrode having a first portion which has sufficient space thereon to form two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 3

A master-slice type semiconductor integrated circuit device comprising: a first transistor; and a second transistor; the first and second transistors being arranged side by side in a first direction; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first gate electrode having a first portion which has sufficient space thereon to form two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; wherein said sufficient space to form the two gate contacts in the first portion of said first gate electrode is located under a second wiring channel which extends in the first direction and which is spaced apart from said first wiring channel in the second direction.

Claim 4

A master-slice type semiconductor integrated circuit device comprising: a first transistor; and a second transistor; the first and second transistors being arranged side by side in a first direction; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first gate electrode having a first portion which has sufficient space thereon to form two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; wherein said sufficient space to form the two gate contacts in the first portion of said first gate electrode is located under a second wiring channel which extends in the first direction and which is spaced apart from said first wiring channel in the second direction.

Claim 5

A master-slice type semiconductor integrated circuit device as claimed in claim 1, wherein: said first gate electrode comprises a third portion in which one gate contact is; said second gate electrode comprises a fourth portion in which one gate contact is made; said first gate electrode comprises a fifth portion connecting the first and third portions to each other; and said second gate electrode comprises a sixth portion connecting the second and fourth portions to each other.

Claim 6

A master-slice type semiconductor integrated circuit device as claimed in claim 3, wherein: the two gate contacts in the first portion of said first gate electrode and said one gate contact in the fourth portion of said second gate electrode are arranged in a line in the first direction; and the two gate contacts in the second portion of the second gate electrode and said one gate contact in the third portion of said first gate electrode are arranged in a line in the first direction.

Claim 7

A master-slice type semiconductor integrated circuit device as claimed in claim 3, wherein: one of the two gate contacts in the first portion of said first gate electrode and one of the two gate contacts in the second portion of said second gate electrode are located under a wiring channel extending in the second direction.

Claim 8

A master-slice type semiconductor integrated circuit device as claimed in claim 3, wherein: the fifth portion of said first gate electrode has a first curved portion connected to the third portion thereof; and the sixth portion of said second gate electrode has a first curved portion connected to the fourth portion thereof.

Claim 9

A master-slice type semiconductor integrated circuit device as claimed in claim 1, wherein: said first transistor comprises first and second impurity diffused regions arranged side by side in the first direction; said second transistor comprises the second impurity diffused region and a third impurity diffused regions arranged side by side in the first direction; and said first, second and third impurity diffused regions have identical conductivity.

Claim 10

A master-slice type semiconductor integrated circuit device as claimed in claim 7, wherein: each of said first, second and third impurity diffused regions have identical widths in the second direction; and the identical widths respectively accommodate three wiring channels extending in the first direction.

Claim 11

A master-slice type semiconductor integrated circuit device comprising: a first transistor arrangement; and a second transistor arrangement; said first and second transistor arrangements having first and second conductivities; wherein each of said first and second transistor arrangements comprises: a first transistor; and a second transistor; said first and second transistors being arranged side by side in a first direction; said first and second transistor respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first and second transistor arrangements being arranged side by side in the second direction; said first gate electrode having a first portion which has sufficient space thereon to form two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 12

A master-slice type semiconductor integrated circuit device comprising: a first transistor arrangement; and a second transistor arrangement; said first and second transistor arrangements having first and second conductivities; wherein each of said first and second transistor arrangements comprises: a first transistor; and a second transistor; said first and second transistors being arranged side by side in a first direction; said first and second transistor respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first and second transistor arrangements being arranged side by side in the second direction; said first gate electrode having a first portion which has sufficient space thereon to form two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 13

A master-slice type semiconductor integrated circuit device as claimed in claim 9, wherein the first and second gate electrodes in the first transistor arrangement are symmetrical with the first and second gate electrodes in the second transistor arrangement with respect to an imaginary boundary line which is located between the first and second transistor arrangements and extends in the first direction.

Claim 14

A master-slice type semiconductor integrated circuit device as claimed in claim 9, wherein the first and second gate electrodes in the first transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the second transistor arrangement.

Claim 15

A master-slice type semiconductor integrated circuit device as claimed in claim 9, further comprising: a first power supply channel extending in the first direction above the first portion of said first gate electrode; and a second power supply channel extending in the second direction above the second portion of said second gate electrode.

Claim 16

A master-slice type semiconductor integrated circuit device as claimed in claim 9, further comprising: a first power supply channel extending in the second direction on first sides of said first and second transistor arrangements; and a second power supply channel extending in the second direction on second sides of said first and second transistor arrangements.

Claim 17

A master-slice type semiconductor integrated circuit device as claimed in claim 13, further comprising a first group of substrate contact areas arranged in a line in the second direction along the first sides of said first and second transistor arrangements; and a second group of substrate contact areas arranged in a line in the second direction along the second sides of said first and second transistor arrangements.

Claim 18

A master-slice type semiconductor integrated circuit device comprising: a first transistor arrangement; a second transistor arrangement; a third transistor arrangement; and a fourth transistor arrangement; said first and second transistor arrangements having first and second conductivities, respectively; said third and fourth transistor arrangements having the first and second conductivities, respectively; each of said first, second, third and fourth transistor arrangements comprising: a first transistor; and a second transistor; said first and second transistors being arranged side by side in a first direction in which the first and third transistor arrangements are arranged side by side and second and fourth transistor arrangements are arranged side by side; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first and second transistor arrangements being arranged side by side in the second direction and said third and fourth transistor arrangements being arranged side by side in the second direction; said first gate electrode having a first portion which is adapted to have formed thereon two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 19

A master-slice type semiconductor integrated circuit device comprising: a first transistor arrangement; a second transistor arrangement; a third transistor arrangement; and a fourth transistor arrangement; said first and second transistor arrangements having first and second conductivities, respectively; said third and fourth transistor arrangements having the first and second conductivities, respectively; each of said first, second, third and fourth transistor arrangements comprising: a first transistor; and a second transistor; said first and second transistors being arranged side by side in a first direction in which the first and third transistor arrangements are arranged side by side and second and fourth transistor arrangements are arranged side by side; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first and second transistor arrangements being arranged side by side in the second direction and said third and fourth transistor arrangements being arranged side by side in the second direction; said first gate electrode having a first portion which is adapted to have formed thereon two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 20

A master-slice type semiconductor integrated circuit device as claimed in claim 15, wherein: said first and second gate electrodes in the first transistor arrangement are symmetrical with the first and second electrodes in the second transistor arrangement with respect to a first imaginary boundary line located between the first and second transistor arrangements and extending in the first direction; and said first and second gate electrodes in the third transistor arrangement are symmetrical with the first and second electrodes in the fourth transistor arrangement with respect to said first imaginary boundary line.

Claim 21

A master-slice type semiconductor integrated circuit device as claimed in claim 16, wherein: said first and second electrodes in the first transistor arrangement are symmetrical with the first and second electrodes in the third transistor arrangement with respect to a second boundary line located between the first and third transistor arrangements and extending in the second direction; and said first and second electrodes in the second transistor arrangement are symmetrical with the first and second electrodes in the fourth transistor arrangement with respect to a third boundary line located between the second and fourth transistor arrangements and extending in the second direction.

Claim 22

A master-slice type semiconductor integrated circuit device as claimed in claim 17, further comprising: a first power supply channel extending in the first direction; and a second power supply channel extending in the first direction; said first and second power supply channels being spaced apart from each other and located outside impurity diffused regions formed in said first, second, third and fourth transistor arrangements.

Claim 23

A master-slice type semiconductor integrated circuit device as claimed in claim 17, further comprising: a first power supply channel extending in the second direction; and a second power supply channel extending in the second direction, said first and second power supply channels being spaced apart from each other and located outside impurity diffused regions formed in said first, second, third and fourth transistor arrangements.

Claim 24

A master-slice type semiconductor integrated circuit device as claimed in claim 15, wherein: the first and second gate electrodes in the first transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the second transistor arrangement; and the first and second gate electrodes in the third transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the fourth transistor arrangement.

Claim 25

A master-slice type semiconductor integrated circuit device as claimed in claim 15, wherein: the first and second gate electrodes in the first transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the third transistor arrangement; and the first and second gate electrodes in the second transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the fourth transistor arrangement.

Claim 26

A master-slice type semiconductor integrated circuit device comprising: a first basic cell; and a second basic cell; each of the first and second basic cells comprising: a first transistor arrangement; a second transistor arrangement; a third transistor arrangement; a fourth transistor arrangement; said first and second transistor arrangements in each of the first and second basic cells having the first and second conductivities, respectively; each of said first, second, third and fourth transistor arrangements in each of the first and second basic cells comprising: a first transistor; and a second transistor; said first and second transistors being arranged side by side in a first direction in which the first and third transistor arrangements are arranged side by side and second and fourth transistor arrangements are arranged side by side and said first and second basic cells are arranged side by side; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first and second transistor arrangements being arranged side by side in the second direction and said third and fourth transistor arrangements being arranged side by side in the second direction; said first gate electrode having a first portion which is adapted to have formed thereon two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 27

A master-slice type semiconductor integrated circuit device comprising: a first basic cell; and a second basic cell; each of the first and second basic cells comprising: a first transistor arrangement; a second transistor arrangement; a third transistor arrangement; a fourth transistor arrangement; said first and second transistor arrangements in each of the first and second basic cells having the first and second conductivities, respectively; each of said first, second, third and fourth transistor arrangements in each of the first and second basic cells comprising: a first transistor; and a second transistor; said first and second transistors being arranged side by side in a first direction in which the first and third transistor arrangements are arranged side by side and second and fourth transistor arrangements are arranged side by side and said first and second basic cells are arranged side by side; said first and second transistors respectively having first and second gate electrodes extending in a second direction perpendicular to the first direction; said first and second transistor arrangements being arranged side by side in the second direction and said third and fourth transistor arrangements being arranged side by side in the second direction; said first gate electrode having a first portion which is adapted to have formed thereon two gate contacts in the first direction; and said second gate electrode having a second portion which is adapted to have formed thereon two gate contacts in the first direction; said first portion of said first gate electrode and said second portion of said second gate electrode being respectively located at end portions of said first gate electrode and said second gate electrode, and are located at different sides of said first gate electrode and said second gate electrode.

Claim 28

A master-slice type semiconductor integrated circuit device as claimed in claim 22, wherein in each of the first and second basic cells: said first and second gate electrodes in the first transistor arrangement are symmetrical with the first and second electrodes in the second transistor arrangement with respect to a first imaginary boundary line located between the first and second transistor arrangements and extending in the first direction; and said first and second gate electrodes in the third transistor arrangement are symmetrical with the first and second electrodes in the fourth transistor arrangement with respect to said first imaginary boundary line, and wherein said first and second basic cells are symmetrical with each other with respect to a second imaginary boundary line located between the first and second basic cells and extending in the first direction.

Claim 29

A master-slice type semiconductor integrated circuit device as claimed in claim 23, further comprising: a first power supply channel extending in the first direction along a first end of the first basic cell; a second power supply channel extending in the first direction along a second end of the first basic cell and a first end of the second basic cell; and a third power supply channel extending in the first direction along a second end of the second basic cell.

Claim 30

A master-slice type semiconductor integrated circuit device as claimed in claim 24, wherein: the second and fourth transistor arrangements of said first basic cell face the first and third transistor arrangements of said second basic cell in the second direction; and the second and fourth transistor arrangements of said first basic cell and the first and third transistor arrangements of said second basic cell have identical conductivities.

Claim 31

A master-slice type semiconductor integrated circuit device as claimed in claim 23, further comprising: a first power supply channel extending in the first direction along a first end of the first basic cell; a second power supply channel extending in the first direction along a second end of the first basic cell; a third power supply channel extending in the first direction along a first end of the second basic cell; and a fourth power supply channel extending in the first direction along a second end of the second basic cell.

Claim 32

A master-slice type semiconductor integrated circuit device as claimed in claim 26, wherein: the second and fourth transistor arrangements of said first basic cell face the first and third transistor arrangements of said second basic cell in the second direction; the second and fourth transistor arrangements of said first basic cell have a first conductivity; and the first and third transistor arrangements of said second basic cell have a second conductivity different from the first conductivity.

Claim 33

A master-slice type semiconductor integrated circuit device as claimed in claim 23, further comprising: a first power supply channel extending in the second direction; and a second power supply channel extending in the second direction, said first and second basic cells being interposed between said first and second power supply channels.

Claim 34

A master-slice type semiconductor integrated circuit device as claimed in claim 28, wherein: the second and fourth transistor arrangements of said first basic cell face the first and third transistor arrangements of said second basic cell in the second direction; and the second and fourth transistor arrangements of said first basic cell and the first and third transistor arrangements of said second basic cell have identical conductivities.

Claim 35

A master-slice type semiconductor integrated circuit device as claimed in claim 28, wherein: the second and fourth transistor arrangements of said first basic cell face the first and third transistor arrangements of said second basic cell in the second direction; the second and fourth transistor arrangements of said first basic cell have a first conductivity; and the first and third transistor arrangements of said second basic cell have a second conductivity different from the first conductivity.

Claim 36

A master-slice type semiconductor integrated circuit device as claimed in claim 22, wherein in each of the first and second basic cells: said first and second gate electrodes in the first transistor arrangement are symmetrical with the first and second electrodes in the third transistor arrangement with respect to a third imaginary boundary line located between the first and third transistor arrangements and extends in the first direction; and said first and second gate electrodes in the second transistor arrangement are symmetrical with the first and second electrodes in the fourth transistor arrangement with respect to a fourth imaginary boundary line located between the second and fourth transistor arrangements and extending in the first direction.

Claim 37

A master-slice type semiconductor integrated circuit device as claimed in claim 22, wherein in each of the first and second basic cells: the first and second gate electrodes in the first transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the third transistor arrangement; and the first and second gate electrodes in the second transistor arrangement are disposed in a manner identical to the first and second gate electrodes in the fourth transistor arrangement.