Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To obtain a gate array having high utility rate by commonly using two N-MOS sources and two P-MOS drains and connecting one N-MOS gate and one P-MOS gate in a basic cell. CONSTITUTION:The sources or drain regions 6 of n-channel MOS transistors TR1, TR2 are commonly used, the drain or source regions 9 of p-channel MOS transistors TR3, TR4 are commonly used, and the gates 1, 3 of n-channel MOS transistor TR1 and p-channel MOS transistor TR3 are connected in circuit as a basic cell of a gate array large scale integrated circuit by master-slice type. When such basic cell is used, almost logic functions can be performed merely by altering the connection layout of the metallic wiring layer, thereby efficiently forming the logic circuit.

Inventors

• 👤 Teruo Kobayashi
• 👤 Haruyuki Tago

Bibliographic Details