Semiconductor integrated circuit with CMOS gate array

Claim 1

A semiconductor integrated circuit comprising: a plurality of p- and n-type semiconductor areas (10P and 10N ) alternately arranged in a row direction; a plurality of p-channel MUS transistor blocks formed in each of said n-type semiconductor areas (10N), each of said plurality of p-channel MOS transistor blocks including a plurality of p-channel MOS transistors (TP11, TP12; Q2, Q4; Q5, Q6; Q7, Q8), arranged in a column direction, whose current paths are serially connected and whose gates are independently formed to extend in a row direction; a plurality of n-channel MOS transistor blocks formed in each of said p-type semiconductor areas (lOP), each of said plurality of n-channel MOS transistor blocks including a plurality of n-channel MOS transistors (TN11, TN12; Ql, Q3; Q9, Q10; Qll, Q12), arranged in a column direction, whose current paths are serially connected and whose gates are independently formed to extend in a row direction; and a plurality of p- and n-type regions (27P and 27N) formed, respectively, in said p- and n-type semiconductor areas (10P and 10N) , characterized in that said p-channel MOS transistor blocks (TP11, TP12; Q2, Q4; Q5, Q6; Q7, Q8) in each of said plurality of n-type semiconductor areas (10N) are arranged in a plurality of columns, said n-channel M OS transistor blocks (TN11, TN12; Ql, Q3; Q9, Q10; Qll, Q12) in each of said plurality of p-type semiconductor areas (10P) are arranged in a plurality of columns, each of said n-type regions (27N) is arranged in a position surrounded by the gate electrodes of the p-channel MOS transistors (Q2, Q4 to Q6) in two of said p-channel MOS transistor blocks adjacent to each other in a row direction, and each of said p-type regions (27P) is arranged in a position surrounded by the gate electrodes of the n-channel MOS transistors (Ql, Q3, Q9, Q10) in two of said n-channel MOS transistor blocks adjacent to each other in a row direction.