Semiconductor integrated circuit with gate-array arrangement

Claim 1

A CMOS gate-array type integrated circuit device having a plurality of cell arrays (Ll, L2, ...) disposed along a row direction (X) on a semidoncutive substrate (32), each of which cell arrays includes a plurality of fundamental cells (Cl, C2, ...) of CMOS construction linearly aligned in a column direction (Y), wherein at least one fundamental cell is used to form each of a plurality of macrocells (60, 80) which serves as unit logical circuit components of an integrated circuit having a desired function, which circuit is constituted by suitably wiring said logical circuit components and providing power source lines, characterized in that: an arbitrary fundamental cell array among said plurality of cell arrays (Ll, L2, ...) is in direct contact with other fundamental cell arrays which are adjacent to each other along the row direction (X), so as to include MOS type transistors (Qpl, Qp2) of the mutually same channel type which are in contact with each other in the row direction (X), which commonly use a semiconductive well region (42) having the opposite conductivity type to that of said substrate (32) and being formed on the surface portion of said substrate (32), and which respectively belong to the two different cell arrays (Ll, L2) which are adjacent to each other; and in that said macrocells include at least one macrocell (60) which is constituted so as to have a particular logical function by at least the two fundamental cells (Cl, C2) which are respectively included in the two mutually neighboring cell arrays (Ll, L2) and which are adjacent to each other along the row direction (X) and which are directly coupled.