US5434441A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness
Assignee: Canon Inc
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Filing: 1994-08-04
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Granted: 1995-07-18
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Expires: 2014-08-04
Abstract
Abstract A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V SS of a low-voltage power supply and the voltage V DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following inequality: T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where K 1 .tbd.ε BOX -1 (Q BN +Q BP ), K 2 .tbd.φ FN +φ FP , ε BOX is the dielectric constant of the base insulation layer, Q BN and Q BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and φ FN and φ FP are pseudo Fermi potentials of the NMOS and PMOS transistors.
Inventors
- 👤 Shunsuke Inoue
- 👤 Toru Koizuki
- 👤 Mamoru Miyawaki
- 👤 Shigetoshi Sugawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:30
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
182 words
A semiconductor device comprising an insulation layer, a thin-film Si layer formed on said insulation layer and having at least one monocrystal Si region formed therein, and an NMOS transistor and a PMOS transistor formed on said at least one monocrystal Si region, wherein a thickness T BOX of said insulation layer at a point where said NMOS and PMOS transistors are formed, a voltage V SS of a first power supply and a voltage V DD of a second power supply to be connected to said NMOS and PMOS transistors, respectively, satisfy a relationship expressed by the following inequality: T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where V DD >V SS , K 1 .tbd.ε BOX -1 (Q BN +Q BP ), K 2 .tbd.φ FN +φ FP , ε BOX is a dielectric constant of said base insulation layer, Q BN and Q BP are respective bulk charges of said NMOS and PMOS transistors when widths of depletion layers of said NMOS and PMOS transistors are maximized, and φ FN and φ FP are pseudo-Fermi potentials of said NMOS and PMOS transistors, respectively.
Claim 2
Dependent Claim
182 words
A semiconductor device comprising an insulation layer, a thin-film Si layer formed on said insulation layer and having at least one monocrystal Si region formed therein, and an NMOS transistor and a PMOS transistor formed on said at least one monocrystal Si region, wherein a thickness T BOX of said insulation layer at a point where said NMOS and PMOS transistors are formed, a voltage V SS of a first power supply and a voltage V DD of a second power supply to be connected to said NMOS and PMOS transistors, respectively, satisfy a relationship expressed by the following inequality: T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where V DD >V SS , K 1 .tbd.ε BOX -1 (Q BN +Q BP ), K 2 .tbd.φ FN +φ FP , ε BOX is a dielectric constant of said base insulation layer, Q BN and Q BP are respective bulk charges of said NMOS and PMOS transistors when widths of depletion layers of said NMOS and PMOS transistors are maximized, and φ FN and φ FP are pseudo-Fermi potentials of said NMOS and PMOS transistors, respectively.
Claim 3
Dependent Claim
233 words
A liquid crystal display in which a switching transistor is used as a pixel electrode switching device, comprising a peripheral device circuit including a semiconductor device, said semiconductor device including an insulation layer, a thin-film Si layer formed on said insulation layer with at least one monocrystal Si region formed therein, and a CMOS inverter including an NMOS transistor and a PMOS transistor formed on said at least one monocrystal Si region, wherein a thickness T BOX of said insulation layer at a point where said NMOS and PMOS transistors are formed, a voltage V SS of a first power supply and a voltage V DD of a second power supply to be connected to said NMOS and PMOS transistors, respectively, satisfy a relationship expressed by the following inequality: T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where V DD >V SS , K 1 .tbd.ε BOX -1 (Q BN +Q BP ), K 2 .tbd.φ FN +φ FP , ε BOX is a dielectric constant of said base insulation layer, Q BN and Q BP are bulk charges when widths of depletion layers of said NMOS and PMOS transistors are maximized, and φ FN and φ FP are pseudo-Fermi potentials of said NMOS and PMOS transistors, and wherein said switching transistor is formed on a display portion of said insulation layer and said CMOS inverter is formed on a drive circuit portion of said insulation layer.
Claim 4
Dependent Claim
233 words
A liquid crystal display in which a switching transistor is used as a pixel electrode switching device, comprising a peripheral device circuit including a semiconductor device, said semiconductor device including an insulation layer, a thin-film Si layer formed on said insulation layer with at least one monocrystal Si region formed therein, and a CMOS inverter including an NMOS transistor and a PMOS transistor formed on said at least one monocrystal Si region, wherein a thickness T BOX of said insulation layer at a point where said NMOS and PMOS transistors are formed, a voltage V SS of a first power supply and a voltage V DD of a second power supply to be connected to said NMOS and PMOS transistors, respectively, satisfy a relationship expressed by the following inequality: T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where V DD >V SS , K 1 .tbd.ε BOX -1 (Q BN +Q BP ), K 2 .tbd.φ FN +φ FP , ε BOX is a dielectric constant of said base insulation layer, Q BN and Q BP are bulk charges when widths of depletion layers of said NMOS and PMOS transistors are maximized, and φ FN and φ FP are pseudo-Fermi potentials of said NMOS and PMOS transistors, and wherein said switching transistor is formed on a display portion of said insulation layer and said CMOS inverter is formed on a drive circuit portion of said insulation layer.
Claim 5
Dependent Claim
16 words
A liquid crystal display according to claim 2, wherein the said switching transistor is PMOS transistor.
Claim 6
Dependent Claim
29 words
A semiconductor device according to claim 1 or claim 2, wherein said monocrystal Si region comprises a thin film obtained by epitaxial growth on a porous Si substrate member.
Claim 7
Dependent Claim
25 words
A semiconductor device according to claim 1 or claim 2, wherein said monocrystal Si region comprises a thin film formed by separation by implanted oxygen.
Claim 8
Dependent Claim
32 words
A semiconductor device according to claim 1 or claim 2, wherein said monocrystal Si region comprises a thin film formed by recrystallizing a polycrystalline or amorphous Si thin film by laser annealing.
Claim 9
Dependent Claim
34 words
A semiconductor device according to claim 1 or claim 2, wherein a leakage current through said NMOS transistor and said PMOS transistor is less than 100 pA for every 1 μm of gate width.
Claim 10
Dependent Claim
21 words
A semiconductor device according to claim 1 or claim 2, wherein a crystal Si substrate is disposed underneath said insulating layer.
Claim 11
Dependent Claim
23 words
A semiconductor device according to claim 1 or claim 2, wherein the value of V DD -V SS is greater than 10 V.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |