Information processing device having electrically erasable programmable read only memory with error check and correction circuit

Claim 2

An information processing device comprising: an array of EEPROM cells; an error check and correction circuit coupled to said array of EEPROM cells for checking for an error in bits forming a data read out from said array of EEPROM cells and for executing an error correction on said error in said bits so that a corrected data is outputted from said error check and correction circuit; a logical circuit coupled to said array of EEPROM cells for outputting an error correction signal for indicating an execution of said error correction when said error check and correction circuit detects and corrects said error in said bits; and address altering means coupled to said array of EEPROM cells for altering a current address where said data is stored in said array of EEPROM cells on the basis of said error correction signal outputted from said logical circuit, said corrected data corrected by said error check and correction circuit is stored in said array of EEPROM cells at a new address which is that address which is altered from said current address by said address altering means.

Claim 3

An information processing device according to claim 1, wherein said address altering means includes: a latch which is set on the basis of said error correction signal for indicating the execution of the error correction; and an adder responsive to said latch being set for adding a predetermined value to a value of said current address in order to output said new address where said corrected data which is corrected by said error check and correction circuit is stored.

Claim 4

An information processing device comprising: a first EEPROM cell array for providing a data memory for storing data therein, said first EEPROM cell array having an error check and correction circuit; a second EEPROM cell array for providing a memory table for storing a table of addresses for said data stored in said first EEPROM cell array; a control circuit coupled to said first and second EEPROM cell arrays, said control circuit producing a table reading signal and a timing signal which is output to said second EEPROM cell array, and said control circuit producing and outputting said timing signal, a data reading signal, and a reading/writing control signal which is output to said first EEPROM cell array; a first address latch coupled to said second EEPROM cell array for supplying a table address to said second EEPROM cell array; a second address latch coupled to said second EEPROM cell array for receiving a current address while said data is stored in said first EEPROM cell array; an error correction latch coupled to said error check and correction circuit in said first EEPROM cell array, said error correction latch is initially cleared by said control circuit and is set by an error correction signal for indicating an execution of an error correction from said error check and correction circuit; an adder coupled to said second address latch and said first EEPROM cell array for producing as an address signal to said first EEPROM cell array, said current address being outputted from said second EEPROM cell array while said error correction latch is cleared and a new address different from said current address while said error correction latch is set; and a data latch coupled to said first EEPROM cell array for latching said data which is read out from said first EEPROM cell array in response to said data reading signal and said reading/writing control signal from said control circuit, said data read out from said first EEPROM cell array is written at said new address of said first EEPROM cell array if said data has been error corrected by said error check and correction circuit, and said new address issued from said adder for indicating where said error corrected data is stored in said first EEPROM cell array being written in said second EEPROM cell array in response to said timing signal from said control circuit.

Claim 5

An information processing device comprising: a first EEPROM cell array for providing a data memory for storing data therein, said first EEPROM cell array having an error check and correction circuit; a second EEPROM cell array for providing a memory table for storing a table of addresses for said data stored in said first EEPROM cell array; a control circuit coupled to said first and second EEPROM cell arrays, said control circuit producing a table reading signal and a timing signal which is output to said second EEPROM cell array, and said control circuit producing and outputting said timing signal, a data reading signal, and a reading/writing control signal which is output to said first EEPROM cell array; a first address latch coupled to said second EEPROM cell array for supplying a table address to said second EEPROM cell array; a second address latch coupled to said second EEPROM cell array for receiving a current address while said data is stored in said first EEPROM cell array; an error correction latch coupled to said error check and correction circuit in said first EEPROM cell array, said error correction latch is initially cleared by said control circuit and is set by an error correction signal for indicating an execution of an error correction from said error check and correction circuit; an adder coupled to said second address latch and said first EEPROM cell array for producing as an address signal to said first EEPROM cell array, said current address being outputted from said second EEPROM cell array while said error correction latch is cleared and a new address different from said current address while said error correction latch is set; and a data latch coupled to said first EEPROM cell array for latching said data which is read out from said first EEPROM cell array in response to said data reading signal and said reading/writing control signal from said control circuit, said data read out from said first EEPROM cell array is written at said new address of said first EEPROM cell array if said data has been error corrected by said error check and correction circuit, and said new address issued from said adder for indicating where said error corrected data is stored in said first EEPROM cell array being written in said second EEPROM cell array in response to said timing signal from said control circuit.