Method for metal deposition without poison via

Claim 1

The method of metal deposition in the manufacture of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing at least one patterned conductive layer for contacting the active elements of said device structures; the surface of said patterned conductive layer structure is irregular with horizontal and vertical components; providing a layer of an insulator over said irregular structure patterned conductive layer; covering said insulator layer with at least one spin-on-glass layer to fill the valleys of said irregular structure and baking and curing said at least one spin-on-glass layer; covering said at least one spin-on-glass layer with a second insulator layer; forming via openings through said at least one spin-on-glass and two insulator layers to said patterned conductive layer; etching within said via openings to remove polymer and oxide formed on the surface of said exposed patterned conductive layer wherein said etching is a radio frequency argon plasma etch with bias voltage of between about 100 and 1000 volts and is performed at a low temperature of between about 0° to 100° C.; thereafter degassing said exposed at least one spin-on-glass layer within said via openings at a high temperature between about 300° to 500° C.; sputtering a metal layer over the surface of said substrate and filling said via openings; and patterning said metal layer to complete said metal deposition in the manufacture of integrated circuits.

Claim 2

The method of metal deposition in the manufacture of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing at least one patterned conductive layer for contacting the active elements of said device structures; the surface of said patterned conductive layer structure is irregular with horizontal and vertical components; providing a layer of an insulator over said irregular structure patterned conductive layer; covering said insulator layer with at least one spin-on-glass layer to fill the valleys of said irregular structure and baking and curing said at least one spin-on-glass layer; covering said at least one spin-on-glass layer with a second insulator layer; forming via openings through said at least one spin-on-glass and two insulator layers to said patterned conductive layer; etching within said via openings to remove polymer and oxide formed on the surface of said exposed patterned conductive layer wherein said etching is a radio frequency argon plasma etch with bias voltage of between about 100 and 1000 volts and is performed at a low temperature of between about 0° to 100° C.; thereafter degassing said exposed at least one spin-on-glass layer within said via openings at a high temperature between about 300° to 500° C.; sputtering a metal layer over the surface of said substrate and filling said via openings; and patterning said metal layer to complete said metal deposition in the manufacture of integrated circuits.

Claim 4

The method of metal deposition in the manufacture of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing at least one patterned conductive layer for contacting the active elements of said device structures; the surface of said patterned conductive layer structure is irregular with horizontal and vertical components; providing a layer of an insulator over said irregular structure patterned conductive layer; covering said insulator layer with at least one spin-on-glass layer to fill the valleys of said irregular structure and baking and curing said at least one spin-on-glass layer; covering said at least one spin-on-glass layer with a second insulator layer; forming via openings through said at least one spin-on-glass and two insulator layers to said patterned conductive layer wherein a residual polymer is formed on the sidewalls of said via openings and wherein an oxide is formed on the exposed surface of said patterned conductive layer; etching within said via openings to remove said residual polymer and said oxide wherein said etching is a radio frequency argon plasma etch with bias voltage of between about 100 and 1000 volts and is performed at a low temperature of between about 0° to 100° C.; thereafter degassing said exposed at least one spin-on-glass layer within said via openings at a high temperature of between about 300° to 500° C.; sputtering a metal layer over the surface of said substrate and filling said via openings; and patterning said metal layer to complete said metal deposition in the manufacture of integrated circuits.

Claim 5

The method of metal deposition in the manufacture of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing at least one patterned conductive layer for contacting the active elements of said device structures; the surface of said patterned conductive layer structure is irregular with horizontal and vertical components; providing a layer of an insulator over said irregular structure patterned conductive layer; covering said insulator layer with at least one spin-on-glass layer to fill the valleys of said irregular structure and baking and curing said at least one spin-on-glass layer; covering said at least one spin-on-glass layer with a second insulator layer; forming via openings through said at least one spin-on-glass and two insulator layers to said patterned conductive layer wherein a residual polymer is formed on the sidewalls of said via openings and wherein an oxide is formed on the exposed surface of said patterned conductive layer; etching within said via openings to remove said residual polymer and said oxide wherein said etching is a radio frequency argon plasma etch with bias voltage of between about 100 and 1000 volts and is performed at a low temperature of between about 0° to 100° C.; thereafter degassing said exposed at least one spin-on-glass layer within said via openings at a high temperature of between about 300° to 500° C.; sputtering a metal layer over the surface of said substrate and filling said via openings; and patterning said metal layer to complete said metal deposition in the manufacture of integrated circuits.