US5180689A — Tapered opening sidewall with multi-step etching …

Claim 1

Independent Claim 159 words

A method for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor comprising: providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover; forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said openings are desired; anisotropically etching into said multilayer insulating layer through a first thickness to form a first opening using said resist masking layer as a mask; isotropic etching through a second thickness portion of said multilayer insulating layer to substantially uniformly enlarge said first opening while using unchanged said resist layer; anisotropically etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said tapered opening with a metal step coverage improvement between about 20 to 60%; and removing the said resist layer.

Claim 2

Independent Claim 159 words

A method for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor comprising: providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover; forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said openings are desired; anisotropically etching into said multilayer insulating layer through a first thickness to form a first opening using said resist masking layer as a mask; isotropic etching through a second thickness portion of said multilayer insulating layer to substantially uniformly enlarge said first opening while using unchanged said resist layer; anisotropically etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said tapered opening with a metal step coverage improvement between about 20 to 60%; and removing the said resist layer.

Claim 3

Dependent Claim 24 words

The method of claim 1 wherein said tapered opening is a contact opening through a borosilicate glass layer to regions within said semiconductor substrate.

Claim 4

Dependent Claim 25 words

The method of claim 1 wherein said tapered opening is a via opening through a spin-on-glass layer to a metallurgy layer under said spin-on-glass layer.

Claim 5

Dependent Claim 29 words

The method of claim 3 wherein said isotropic etching uses a dry ambient of the group consisting of NF 3 and CF 4 with appropriate time and temperature conditions.

Claim 6

Dependent Claim 25 words

The method of claim 2 wherein said isotropic etching uses a wet etchant of NH 4 F and HF, with appropriate time and temperature conditions.

Claim 7

Dependent Claim 45 words

The method of claim 2 wherein said borosilicate glass is a borophosphosilicate glass having a thickness between about 8000 to 20,000 Angstroms, the said first thickness is between about 1000 to 5000 Angstroms and the said second thickness is between about 1000 to 5000 Angstroms.

Claim 8

Dependent Claim 45 words

The method of claim 3 wherein said spin-on-glass is a cured silicate type having a thickness of between about 1000 to 4000 Angstroms, the said first thickness is between about 1000 to 5000 Angstroms and the second thickness is between about 1000 to 5000 Angstroms.

Claim 9

Dependent Claim 45 words

The method of claim 3 wherein said spin-on-glass is a cured siloxane type having a thickness of between about 1000 to 4000 Angstroms, the said first thickness is between about 1000 to 5000 Angstroms and the second thickness is between about 1000 to 5000 Angstroms.

Claim 10

Dependent Claim 39 words

The method of claim 1 wherein said resist masking layer is a novolac, said anisotropically etching is accomplished using CHF 3 ambient whereby there is substantially no erosion of said resist masking layer during said anisotropically and isotropic etching.

Claim 11

Dependent Claim 16 words

The method of claim 1 wherein said integrated circuit includes metal oxide semiconductor field effect transistors.

Claim 12

Dependent Claim 12 words

The method of claim 1 wherein said integrated circuit includes bipolar transistors.

Claim 13

Dependent Claim 167 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said silicate glass layer having openings therein in the areas where the said contact openings are desired; anisotropically etching into said silicate glass layer through a first thickness to form a first opening using said resist masking layer as a mask; isotropic etching through a second thickness portion of said silicate glass layer to substantially uniformly enlarge said first opening while using unchanged said resist layer; anisotropically etching through the remaining thickness of said silicate glass layer to the semiconductor substrate to form said tapered opening with a metal step coverage improvement between about 20 to 60% ; and removing the said resist layer.

Claim 14

Dependent Claim 167 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said silicate glass layer having openings therein in the areas where the said contact openings are desired; anisotropically etching into said silicate glass layer through a first thickness to form a first opening using said resist masking layer as a mask; isotropic etching through a second thickness portion of said silicate glass layer to substantially uniformly enlarge said first opening while using unchanged said resist layer; anisotropically etching through the remaining thickness of said silicate glass layer to the semiconductor substrate to form said tapered opening with a metal step coverage improvement between about 20 to 60% ; and removing the said resist layer.

Claim 15

Dependent Claim 23 words

The method of claim 12 wherein said isotropic etching uses a wet etchant of NH 4 F and HF, with appropriate temperature/time conditions.

Claim 16

Dependent Claim 45 words

The method of claim 12 wherein said silicate glass is a borophosphosilicate glass having a thickness between about 8000 to 20,000 Angstroms, the said first thickness is between about 1000 to 5000 Angstroms and the said second thickness is between about 1000 to 5000 Angstroms.

Claim 17

Dependent Claim 44 words

The method of claim 12 wherein said resist masking layer is a novolac, said anisotropically etching is accomplished using CHF 3 , CF 4 and argon ambient whereby there is substantially no erosion of said resist masking layer during said anisotropically and isotropic etching.

Claim 18

Dependent Claim 174 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a composite layer composed of a silicon oxide layer, spin-on-glass and a silicon oxide layer, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said composite layer having openings therein in the areas where the said openings are desired; anisotropically etching into said composite layer through a first thickness to form a first opening using said resist masking layer as a mask; isotropic etching through a second thickness portion of said composite layer to substantially uniformly enlarge said first opening while using unchanged said resist layer; anisotropically etching through the remaining thickness of said composite layer to the desired conductive layer forming part of said device elements to form said tapered opening with a metal step coverage improvement between about 20 to 60%; and removing the said resist layer.

Claim 19

Dependent Claim 174 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a composite layer composed of a silicon oxide layer, spin-on-glass and a silicon oxide layer, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said composite layer having openings therein in the areas where the said openings are desired; anisotropically etching into said composite layer through a first thickness to form a first opening using said resist masking layer as a mask; isotropic etching through a second thickness portion of said composite layer to substantially uniformly enlarge said first opening while using unchanged said resist layer; anisotropically etching through the remaining thickness of said composite layer to the desired conductive layer forming part of said device elements to form said tapered opening with a metal step coverage improvement between about 20 to 60%; and removing the said resist layer.

Claim 20

Dependent Claim 30 words

The method of claim 16 wherein said isotropic etching uses a dry etchant of the group consisting of NF 3 , CCF 4 and CHF 3 with appropriate temperature/time conditions.

Claim 21

Dependent Claim 46 words

The method of claim 16 wherein said spin-on-glass is a cured silicate type glass having a thickness between about 1000 to 3000 Angstroms, the said first thickness is between about 1000 to 5000 Angstroms and the said second thickness is between about 1000 to 5000 Angstroms.

Claim 22

Dependent Claim 46 words

The method of claim 16 wherein said spin-on-glass is a cured siloxane type glass having a thickness between about 1000 to 5000 Angstroms, the said first thickness is between about 1000 to 5000 Angstroms and the said second thickness is between about 1000 to 5000 Angstroms.

Claim 23

Dependent Claim 44 words

The method of claim 16 wherein said resist masking layer is a novolac, said anisotropically etching is accomplished using CHF 3 , CF 4 and argon plasma whereby there is substantially no erosion of said resist masking layer during said anisotropically and isotropic etching.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-01-19	1996-07-20	1997-01-19	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-01-19	2000-07-20	2001-01-19	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-01-19	2004-07-20	2005-01-19	$7700.00	Window Closed / Lapsed

Tapered opening sidewall with multi-step etching process

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