US4832788A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a tapered via hole in polyimide
Assignee: Unisys Corp
•
Filing: 1987-05-21
•
Granted: 1989-05-23
•
Expires: 2007-05-21
Abstract
Abstract A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of: disposing a layer of SiO 2 on the polyimide layer and a layer of photoresist on the SiO 2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO 2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO 2 ; and repeating the etching step and enlarging step a predetermined number of times.
Inventors
- 👤 Michael H. Nemiroff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:16
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/286; H10P50/287; H10P50/73; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/95; Y10S438/978
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
152 words
A method of fabricating a stepped via hole in a polyimide layer of an integrated circuit, including the steps of: disposing a layer of SiO 2 on said polyimide layer and a layer of photoresist on said SiO 2 layer such that said layers define an opening which exposes a region of said polyimide layer for said via hole; etching said exposed polyimide region partway through said polyimide layer, while simultaneously etching back said photoresist on the sidewalls of said opening to thereby uncover a strip of said SiO 2 adjacent the perimeter of said exposed polyimide region; enlarging the exposed region of said polyimide by etching said uncovered strip of said SiO 2 ; and subsequently, forming a step in said polyimide layer by repeating said etching step to remove additional polyimide from the enlarged exposed polyimide region and to further etch back said photoresist on the sidewalls of said opening.
Claim 2
Independent Claim
152 words
A method of fabricating a stepped via hole in a polyimide layer of an integrated circuit, including the steps of: disposing a layer of SiO 2 on said polyimide layer and a layer of photoresist on said SiO 2 layer such that said layers define an opening which exposes a region of said polyimide layer for said via hole; etching said exposed polyimide region partway through said polyimide layer, while simultaneously etching back said photoresist on the sidewalls of said opening to thereby uncover a strip of said SiO 2 adjacent the perimeter of said exposed polyimide region; enlarging the exposed region of said polyimide by etching said uncovered strip of said SiO 2 ; and subsequently, forming a step in said polyimide layer by repeating said etching step to remove additional polyimide from the enlarged exposed polyimide region and to further etch back said photoresist on the sidewalls of said opening.
Claim 3
Dependent Claim
31 words
A method according to claim 1 wherein said polyimide layer is etched completely through by performing said enlarging step at least twice and following each such step with said etching step.
Claim 4
Dependent Claim
32 words
A method according to claim 1 wherein said polyimide layer is at least 2.0 microns thick, and wherein each performance of said etching step removes only 0.2-1.5 microns of said polyimide layer.
Claim 5
Dependent Claim
53 words
A method according to claim 1 wherein the etching of said polyimide occurs perpendicular to said layers substantially faster than it occurs parallel to said layers so said stepped via hole is fabricated with a narrow end which nearly matches the region of said polyimide that is initially exposed by said disposing step.
Claim 6
Dependent Claim
27 words
A method according to claim 1 wherein said etching and enlarging steps are performed by reactive ion etching with respective ions that are different from each other.
Claim 7
Dependent Claim
73 words
A method according to claim 1 wherein said polyimide layer is etched completely through by repeating said etching and enlarging steps a predetermined number of times; and thereafter, a patterned metal layer is disposed with a first thickness on said polyimide layer, and simultaneously is disposed on the sidewalls of said exposed polyimide region which remains after said etching steps with a second thickness that is at least 40% of said first thickness.
Claim 8
Dependent Claim
21 words
A method according to claim 1 wherein said SiO 2 layer is less than one-fifth the thickness of said photoresist layer.
Claim 9
Independent Claim
158 words
A method of fabricating a stepped via hole in an organic insulating layer of an integrated circuit, including the steps of: disposing an inorganic mask layer on said organic insulating layer and an organic mask layer on said inorganic mask layer such that said mask layers define an opening which exposes a region of said insulating layer for said via hole; etching said exposed insulating region partway through, while simultaneously etching back said organic mask layer on the sidewalls of said opening to thereby uncover a strip of said inorganic mask layer at the perimeter of said exposed insulating region; enlarging the exposed region of said insulating layer by etching said uncovered strip of said inorganic mask layer; and subsequently, forming a step in said insulating layer by repeating said etching step to remove additional organic insulating material from the enlarged exposed region and to further etch back said organic mask layer on the sidewalls of said opening.
Claim 10
Independent Claim
158 words
A method of fabricating a stepped via hole in an organic insulating layer of an integrated circuit, including the steps of: disposing an inorganic mask layer on said organic insulating layer and an organic mask layer on said inorganic mask layer such that said mask layers define an opening which exposes a region of said insulating layer for said via hole; etching said exposed insulating region partway through, while simultaneously etching back said organic mask layer on the sidewalls of said opening to thereby uncover a strip of said inorganic mask layer at the perimeter of said exposed insulating region; enlarging the exposed region of said insulating layer by etching said uncovered strip of said inorganic mask layer; and subsequently, forming a step in said insulating layer by repeating said etching step to remove additional organic insulating material from the enlarged exposed region and to further etch back said organic mask layer on the sidewalls of said opening.
References Cited (Backward Citations)
US4472240A
Cited
US4514252A
Cited
US4495220A
Cited
JPS60140720A
Cited
US4487652A
Cited
US4592802A
Cited
US4484979A
Cited
US4522681A
Cited
US4560436A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |