Post passivation mask ROM programming method

Claim 1

A method of manufacturing a Read Only Memory device with an array of cells comprising: a) forming a plurality of closely spaced line regions with a first impurity type in and adjacent to the surface of a semiconductor substrate having a surface and a background impurity of a second opposite type, b) forming a thin insulating layer on said surface of said substrate, c) forming a plurality of closely spaced, parallel, thin, electrically conductive lines on said thin insulating layer arranged orthogonally relative to said line regions, d) forming a thin glass insulating layer over said conductive lines having a thickness of less than or equal to about 3000 Å, said glass insulating layer comprising a sublayer of undoped USG glass having a thickness of about 1000 Å and an overlayer of doped glass having a thickness of between about 1000 Å and about 2000 Å. e) reflowing said glass insulating layer to provide planarization thereof, f) forming contacts to said cells through said insulating layer after reflowing thereof, g) forming a metal layer on said glass insulating layer, h) depositing a resist layer on said metal layer, i) exposing said resist layer with a metal pattern, etching through said resist layer to form patterned metal and removing said resist layer, j) depositing a second resist layer onto said patterned metal, and exposing said second resist layer with a custom code pattern, k) developing said resist layer into a mask, l) etching exposed areas of said insulating layer to form openings exposing selected areas of said conductive lines, m) implanting impurity ions into said substrate adjacent to said conductive lines through said openings in said insulating layer, n) removing said resist layer, o) passivating said device with a thin layer, p) activating said implanted impurity ions by annealing said device at a temperature between about 420° C. and about 520° C. in gas comprising nitrogen gas N 2 alone or with hydrogen gas H 2 , whereby the metallurgy and the electrical contacts to the substrate, line regions and conductor lines are protected from adverse effect during annealing.

Claim 2

A method of manufacturing a Read Only Memory device with an array of cells comprising: a) forming a plurality of closely spaced line regions with a first impurity type in and adjacent to the surface of a semiconductor substrate having a surface and a background impurity of a second opposite type, b) forming a thin insulating layer on said surface of said substrate, c) forming a plurality of closely spaced, parallel, thin, electrically conductive lines on said thin insulating layer arranged orthogonally relative to said line regions, d) forming a thin glass insulating layer over said conductive lines having a thickness of less than or equal to about 3000 Å, said glass insulating layer comprising a sublayer of undoped USG glass having a thickness of about 1000 Å and an overlayer of doped glass having a thickness of between about 1000 Å and about 2000 Å. e) reflowing said glass insulating layer to provide planarization thereof, f) forming contacts to said cells through said insulating layer after reflowing thereof, g) forming a metal layer on said glass insulating layer, h) depositing a resist layer on said metal layer, i) exposing said resist layer with a metal pattern, etching through said resist layer to form patterned metal and removing said resist layer, j) depositing a second resist layer onto said patterned metal, and exposing said second resist layer with a custom code pattern, k) developing said resist layer into a mask, l) etching exposed areas of said insulating layer to form openings exposing selected areas of said conductive lines, m) implanting impurity ions into said substrate adjacent to said conductive lines through said openings in said insulating layer, n) removing said resist layer, o) passivating said device with a thin layer, p) activating said implanted impurity ions by annealing said device at a temperature between about 420° C. and about 520° C. in gas comprising nitrogen gas N 2 alone or with hydrogen gas H 2 , whereby the metallurgy and the electrical contacts to the substrate, line regions and conductor lines are protected from adverse effect during annealing.

Claim 18

A method of manufacturing a Read Only Memory device with an array of cells comprising: a) forming a plurality of closely spaced line regions with a first impurity type in and adjacent to the surface of a semiconductor substrate having a surface and a background impurity of a second opposite type, b) forming a thin insulating layer on said surface of said substrate, c) forming a plurality of closely spaced, parallel, thin, electrically conductive lines on said thin insulating layer arranged orthogonally relative to said line regions, d) forming a thin glass insulating layer over said conductive lines having a thickness of less than or equal to about 3000 Å, said thin glass insulating layer comprising a sublayer of undoped USG glass having a thickness of about 1000 Å and an overlayer of doped BPSG glass having a thickness of between about 1000 Å and about 2000 Å, e) reflowing said glass insulating layer to provide planarization thereof, f) forming contacts to said cells through said insulating layer after reflowing thereof, g) forming a metal layer on said glass insulating layer, h) depositing a resist layer on said metal layer, i) exposing said resist layer with a metal pattern, etching through said resist layer to form patterned metal and removing said resist layer, and etching substantially all of said doped BPSG glass layer, leaving behind said USG layer, j) depositing a second resist layer onto said patterned metal, and exposing said second resist layer with a custom code pattern, k) developing said resist layer into a mask, l) etching exposed areas of said insulating layer to form openings exposing selected areas of said conductive lines, m) implanting impurity ions into said substrate adjacent to said conductive lines through said openings in said insulating layer, n) removing said resist layer, o) passivating said device with a thin layer, p) activating said implanted impurity ions by annealing said device at a temperature between about 420° C. and about 520° C. in a gas comprising nitrogen gas N 2 alone or in combination with hydrogen gas H 2 , whereby the metallurgy and the electrical contacts to the substrate, line regions and conductor lines are protected from adverse effect during annealing.

Claim 19

A method of manufacturing a Read Only Memory device with an array of cells comprising: a) forming a plurality of closely spaced line regions with a first impurity type in and adjacent to the surface of a semiconductor substrate having a surface and a background impurity of a second opposite type, b) forming a thin insulating layer on said surface of said substrate, c) forming a plurality of closely spaced, parallel, thin, electrically conductive lines on said thin insulating layer arranged orthogonally relative to said line regions, d) forming a thin glass insulating layer over said conductive lines having a thickness of less than or equal to about 3000 Å, said thin glass insulating layer comprising a sublayer of undoped USG glass having a thickness of about 1000 Å and an overlayer of doped BPSG glass having a thickness of between about 1000 Å and about 2000 Å, e) reflowing said glass insulating layer to provide planarization thereof, f) forming contacts to said cells through said insulating layer after reflowing thereof, g) forming a metal layer on said glass insulating layer, h) depositing a resist layer on said metal layer, i) exposing said resist layer with a metal pattern, etching through said resist layer to form patterned metal and removing said resist layer, and etching substantially all of said doped BPSG glass layer, leaving behind said USG layer, j) depositing a second resist layer onto said patterned metal, and exposing said second resist layer with a custom code pattern, k) developing said resist layer into a mask, l) etching exposed areas of said insulating layer to form openings exposing selected areas of said conductive lines, m) implanting impurity ions into said substrate adjacent to said conductive lines through said openings in said insulating layer, n) removing said resist layer, o) passivating said device with a thin layer, p) activating said implanted impurity ions by annealing said device at a temperature between about 420° C. and about 520° C. in a gas comprising nitrogen gas N 2 alone or in combination with hydrogen gas H 2 , whereby the metallurgy and the electrical contacts to the substrate, line regions and conductor lines are protected from adverse effect during annealing.