Digital data apparatus for transferring data between a byte-wide digital data bus and a four byte-wide digital data bus

Claim 1

Digital data apparatus comprising: a first byte-wide digital data bus; a second four byte-wide digital data bus; a byte-wide first-in, first-out (FIFO) memory connected to said first byte-wide digital data bus for storing sequential bytes of data from said first byte-wide digital data bus; first, second, third, and fourth byte-wide funnel registers which are connected in parallel and have inputs connected to said four byte-wide FIFO memory and also having respective outputs; a four byte-wide data register having first, second, third and fourth byte-wide inputs respectively connected to the outputs of said first, second, third and fourth byte-wide funnel registers and having a four byte-wide output connected to said second four byte-wide digital data bus; and control means for controlling said digital data apparatus wherein one to four bytes of digital data are transferred from said second four byte-wide digital data bus to said four byte-wide data register in parallel with the transfer of bytes of digital data stored in said FIFO memory to said first byte-wide digital data bus. wherein said control means selectively controls the transfer of digital data from said second four byte-wide digital data bus to said first byte-wide digital data bus by way of said four byte-wide data register, said first, second, third and fourth funnel registers, and said FIFO memory; wherein said transferred digital data can be a long word of four bytes, a short word of two bytes, and an odd or even data byte; and wherein said control means controls (a) in a long word mode in which four bytes of a long word are transferred in parallel from said second four byte-wide digital data bus to said four byte-wide data register, are transferred in parallel from said four byte-wide data register to said first, second, third and fourth funnel registers, are transferred sequentially from said funnel registers to said FIFO memory and are transferred sequentially from said FIFO memory to said first byte-wide digital data bus; (b) in a short word mode, in which two bytes of a short word are transferred in parallel from said second four byte-wide digital data bus to said four byte-wide data register, are transferred in parallel from said four byte-wide data register to said first and second funnel registers, are transferred sequentially from said first and second funnel registers to said FIFO memory, and are transferred sequentially from said FIFO memory to said first byte-wide digital data but; (c) in an odd or even data byte mode, in which a data byte is transferred from said second four byte-wide digital data bus to said four byte-wide data register; is transferred to said second funnel register, if an even data byte is to be transferred or is transferred to said first funnel register if an odd data byte is to be transferred; is transferred to said FIFO register from said second funnel register or from said first funnel register, respectively, and from said FIFO memory to said first byte-wide digital data bus.