US5226010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for simultaneous, interleaved access of multiple memories by multiple ports
Assignee: EMC Corp
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Filing: 1992-10-22
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Granted: 1993-07-06
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Expires: 2012-10-22
Abstract
Abstract A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.
Inventors
- 👤 Joseph S. Glider
- 👤 Kaushik S. Shah
- 👤 Edward E. Asato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:11
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1647
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
101 words
A memory buffering system comprising: a plurality of buffer memories; first and second data ports; multiplexing means for selectively coupling each of said data ports to each of said buffer memories; and sequencing means for providing control signals to said multiplexing means to alternately couple said data ports to each of said memories for the transfer of a first block of data into a first one of said buffer memories and concurrently transferring a second block of data out of a second one of said buffer memories, each of said memories having a capacity of a plurality of blocks of data.
Claim 2
Dependent Claim
101 words
A memory buffering system comprising: a plurality of buffer memories; first and second data ports; multiplexing means for selectively coupling each of said data ports to each of said buffer memories; and sequencing means for providing control signals to said multiplexing means to alternately couple said data ports to each of said memories for the transfer of a first block of data into a first one of said buffer memories and concurrently transferring a second block of data out of a second one of said buffer memories, each of said memories having a capacity of a plurality of blocks of data.
Claim 3
Dependent Claim
47 words
The memory buffering system of claim 1 further comprising: a plurality of address bus inputs, one associated with each of said data ports; and multiplexing means for coupling each of said address bus inputs to one of said memories to which its corresponding data port is coupled.
Claim 4
Dependent Claim
21 words
The memory buffering system of claim 2 further comprising a separate address counter coupled to each of said address bus inputs.
Claim 5
Dependent Claim
32 words
The memory buffering system of claim 2 further comprising a number of bits of each said address bus sufficient to address said plurality of memories coupled as inputs to said sequencing means.
Claim 6
Independent Claim
97 words
A method for accessing a memory buffering system having a plurality of memories and first and second data ports, comprising the steps of: selectively coupling each of said data ports to each of said memories; alternately coupling said data ports to each of said memories for the transfer of a block of data, each of said memories having a capacity of a plurality of blocks of data; inputting data through the first port at the full bandwidth of the first port and simultaneously outputting data through the second port at the full bandwidth of the second port.
Claim 7
Independent Claim
97 words
A method for accessing a memory buffering system having a plurality of memories and first and second data ports, comprising the steps of: selectively coupling each of said data ports to each of said memories; alternately coupling said data ports to each of said memories for the transfer of a block of data, each of said memories having a capacity of a plurality of blocks of data; inputting data through the first port at the full bandwidth of the first port and simultaneously outputting data through the second port at the full bandwidth of the second port.
Claim 8
Dependent Claim
40 words
The method of claim 6 further comprising the step of coupling each of a plurality of address bus inputs, one associated with each of said data ports, to one of said memories to which its corresponding data port is coupled.
Claim 9
Dependent Claim
26 words
The memory buffering system of claim 1 wherein said sequencing means interleaves blocks of data from different ones of said ports in each of said memories.
Claim 10
Dependent Claim
26 words
The memory buffering system of claim 1 wherein said first port is coupled to a computer and said second port is coupled to a disk drive.
Claim 11
Dependent Claim
44 words
The memory buffering system of claim 1 further comprising a third data port, wherein said sequencing means provides control signals to couple said third data port to a different one of said buffer memories than said first and second data ports are coupled to.
References Cited (Backward Citations)
US5097118A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |