US4847759A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Register selection mechanism and organization of an instruction prefetch buffer
Assignee: International Business Machines Corp
•
Filing: 1987-08-04
•
Granted: 1989-07-11
•
Expires: 2007-08-04
Abstract
Abstract A register selection mechanism for an instruction prefetch buffer which allows instructions having different lengths to be accessed on the instruction boundaries. The instruction prefetch buffer comprises a one-port-write, two-port-read array (10). Address generation and control logic (16) is responsive to a read pointer (15) for controlling access to odd and oven addresses in the array. Additional logic may be provided to provide an indication that the instruction prefetch buffer is empty.
Inventors
- 👤 Vojin G. Oklobdzija
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
222 words
An instruction prefetch buffer connected to an n-bit bus and an output n-bit bus comprising: an array having one n-bit input write port and two m-bit output read ports where n=2 m, said n-bit input port being connected to said input n-bit bus for receiving an n-bit, two m-bit or a mixture of portions of n-bit and m-bit instructions from a main memory for writing into said array and two m-bit output ports each providing respectively m-bits of an instruction read out of said array, said array storing a mixture of n-bit and m-bit instructions which start on m-bit address boundaries within said array; a write pointer register for temporarily storing a first binary number which points to an n-bit location in said array where n bits from said main memory is to be written, said array being connected to said write pointer register and responsive to said first binary number for writing an instruction at said location; and address generation and control logic means connected to said array for accessing the instructions in said array on m-bit address boundaries within said array and providing m-bit instructions on the most significant bit lines of said output n-bit bus and combining two m-bit outputs from said two m-bit output ports in the proper order to form an n-bit instruction on said output bus.
Claim 2
Dependent Claim
222 words
An instruction prefetch buffer connected to an n-bit bus and an output n-bit bus comprising: an array having one n-bit input write port and two m-bit output read ports where n=2 m, said n-bit input port being connected to said input n-bit bus for receiving an n-bit, two m-bit or a mixture of portions of n-bit and m-bit instructions from a main memory for writing into said array and two m-bit output ports each providing respectively m-bits of an instruction read out of said array, said array storing a mixture of n-bit and m-bit instructions which start on m-bit address boundaries within said array; a write pointer register for temporarily storing a first binary number which points to an n-bit location in said array where n bits from said main memory is to be written, said array being connected to said write pointer register and responsive to said first binary number for writing an instruction at said location; and address generation and control logic means connected to said array for accessing the instructions in said array on m-bit address boundaries within said array and providing m-bit instructions on the most significant bit lines of said output n-bit bus and combining two m-bit outputs from said two m-bit output ports in the proper order to form an n-bit instruction on said output bus.
Claim 3
Dependent Claim
72 words
An instruction prefetch buffer as recited in claim 1 wherein said array comprises first and second subarrays of m-bit registers, said first subarray storing instructions which are addressed with odd addresses and said second subarray storing instructions which are addressed with even addresses, said array further comprising odd address decoding means for decoding odd addresses for said first subarray and even address decoding means for decoding even addresses for said second subarray.
Claim 4
Dependent Claim
128 words
The instruction prefetch buffer as recited in claim 2 wherein said address generation and control logic means comprises: a read pointer register for temporarily storing a second binary number which points to an n-bit location in said array where an instruction is to be read; address generating means responsive to said second binary number in said read pointer register for generating odd and even addresses supplied, respectively, to said odd and even address decoding means; and multiplexer means connected to said two output ports of said array and controlled by the least significant bit of said binary number in said read pointer register for reversing the order of the output of said array or not, depending on whether an instruction begins at an even or odd address, respectively.
Claim 5
Dependent Claim
174 words
An instruction prefetch buffer as recited in claim 3 further comprising means responsive to said write and read pointer registers for providing an output indicating that said instruction prefetch buffer is empty, said means comprising: first equality detecting means connected to said write and read pointer registers for providing an output when addresses corresponding to said first and second binary numbers are equal; incrementing means connected to said read pointer register for adding one to said second binary number and providing an incremented output; second equality detecting means connected to said write pointer register and said incrementing means for providing an output when addresses corresponding to said first binary number and said incremented output are equal; an AND gate enabled when an instruction is an n-bit instruction and connected to provide as an output the output of said second equality detecting means when enabled; and an OR gate connected to the outputs of said first equality detecting means and said AND gate to provide an output indicative of said instruction prefetch buffer being empty.
Claim 6
Dependent Claim
170 words
An instruction prefetch buffer as recited in claim 3 wherein said address generating means comprises: incrementer means connected to said read pointer register for adding one to said second binary number to provide an incremented output; and first and second multiplexers each having first and second inputs and a single output, the output of said first multiplexer being connected to said odd address decoding means and the output of said second multiplexer being connected to said even address decoding means, said incremented ouput from said incrementer means being connected to the second and first inputs, respectively, of said first and second multiplexers, and said first and second inputs, respectively, of said first and second multiplexers being connected to said read pointer register, said first and second multiplexers being controlled by the least significant bit of said second binary number in said read pointer register to supply as their respective outputs their first or second inputs depending on whether the least significant bit is a binary zero or a binary one.
References Cited (Backward Citations)
US3739352A
Cited
US4070657A
Cited
US4135242A
Cited
US4219874A
Cited
US4375665A
Cited
US4447878A
Cited
US4489395A
Cited
US4309754A
Cited
US4347567A
Cited
US4443846A
Cited
US4569018A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |