Information processor

Claim 2

In an information processor including a main memory having a plurality of memory locations for storing and reading operand information and program instruction information, an N bit architecture central processing unit, and a memory bus for transferring operand information and program instruction information from the main memory to the central processing unit; the improvement comprising said memory bus having a width of 2N bits, and said central processing unit comprising: a scratch pad memory including at least one operand buffer having an N bit width and at least two instruction buffers each having an N bit width; a microprogram control section including at least one microprogram which is selectable based on information stored in said scratch pad memory; an N bit data bus connected to said scratch pad memory and said microprogram control section; first means for causing N bit operand information to be read from said main memory onto the memory bus and 2N bits of information including instructions to be read at one time from said main memory onto the memory bus, and for causing said N bit operand information read from the main memory to be written into said operand buffer and said 2N bits of information including instructions read from the main memory to be written into said instruction buffers; a selector connected between said memory bus and said scratch pad memory; and second means for causing said selector to select N bits of said memory bus when said first means causes N bit operand information to be read onto the memory bus from said main memory to enable said N bit operand information read from said main memory to be written into said operand buffer, and for causing said selector to select 2N bits of said memory bus when said first means causes 2N bits of information including instructions to be read at one time onto the memory bus from said main memory, N bits of said memory bus being selected to enable N bits of said 2N bits of information on said memory bus read from said main memory to be written into one of said instruction buffers and a further N bits of said memory bus being selected to enable a further N bits of said 2N bits of information on said memory bus read from said main memory to be written into the other of said instruction buffers.

Claim 3

In an information processor according to claim 1, wherein the improvement further comprises said microprogram control section including means for storing said at least one microprogram comprised of microinstructions, means for reading microinstructions from said means for storing and means for holding a microinstruction read from said means for storing, and means for reading N bit information from said instruction buffers in said scratch pad memory to said N bit data bus, said microprogram control section means for reading selecting a start address of a microprogram contained in said means for storing in accordance with an operation code included in the N bit information contained in one of said instruction buffers and reading the first microinstruction of said selected microprogram to said means for holding.

Claim 4

In an information processor according to claim 2, wherein the improvement further comprises said first means including means for causing N bit information to be read from said main memory into said one of said instruction buffers while said microinstruction held in said means for holding is being executed.

Claim 5

In an information processor according to claim 2, wherein the improvement further comprises said microprogram control section means for reading including means for reading a subsequent microinstruction of the selected microprogram while said first microinstruction is being executed.

Claim 6

In an information processor according to claim 4, wherein the improvement further comprises said instruction buffer reading means including means for reading N bit information from the other of said instruction buffers to said N bit data bus while said subsequent microinstruction is being executed.

Claim 7

In an information processor including a main memory having a plurality of memory locations for storing and reading operand information and program instruction information, an N bit architecture central processing unit, and a memory bus for transferring operand information and instruction information from the main memory to the central processing unit; the improvement comprising said memory bus having a width of 2N bits, and said central processing unit comprising: an instruction buffer having at least two N bit widths; a microprogram control section including at least one microprogram which is selectable based on information stored in said instruction buffer; an N bit data bus connected to said instruction buffer and said microprogram control section; a scratch pad memory including at least one operand buffer having an N bit width; first means for causing N bit operand information to be read from said main memory onto the memory bus and 2N bits of information including instructions to be read at one time from said main memory onto the memory bus, and for causing said N bit operand information read from the main memory to be written into said operand buffer and said 2N bits of information including instructions read from the main memory to be written into said instruction buffer; a first selector connected between said memory bus and said instruction buffer; a second selector connected between said memory bus and said scratch pad memory; and second means for causing said second selector to select N bits of said memory bus when said first means causes N bit operand information to be read from said main memory to enable said N bit operand information read from said main memory to be written into said operand buffer, and for causing said first selector to select 2N bits of said memory bus when said first means causes 2N bits of information including instructions to be read at one time onto the memory bus from said main memory, N bits of said memory bus being selected to enable N bits of said 2N bits of information on said memory bus read from said main memory to be written into one of the N bit widths of said instruction buffer and a further N bits of said memory bus being selected to enable a further N bits of said 2N bits of information on said memory bus read from said main memory to be written into the other of the N bit widths of said instruction buffer.

Claim 8

In an information processor including a main memory having a plurality of memory locations for storing and reading operand information and program instruction information, an N bit architecture central processing unit, and a memory bus for transferring operand information and instruction information from the main memory to the central processing unit; the improvement comprising said memory bus having a width of 2N bits, and said central processing unit comprising: an instruction buffer having at least two N bit widths; a microprogram control section including at least one microprogram which is selectable based on information stored in said instruction buffer; an N bit data bus connected to said instruction buffer and said microprogram control section; a scratch pad memory including at least one operand buffer having an N bit width; first means for causing N bit operand information to be read from said main memory onto the memory bus and 2N bits of information including instructions to be read at one time from said main memory onto the memory bus, and for causing said N bit operand information read from the main memory to be written into said operand buffer and said 2N bits of information including instructions read from the main memory to be written into said instruction buffer; a first selector connected between said memory bus and said instruction buffer; a second selector connected between said memory bus and said scratch pad memory; and second means for causing said second selector to select N bits of said memory bus when said first means causes N bit operand information to be read from said main memory to enable said N bit operand information read from said main memory to be written into said operand buffer, and for causing said first selector to select 2N bits of said memory bus when said first means causes 2N bits of information including instructions to be read at one time onto the memory bus from said main memory, N bits of said memory bus being selected to enable N bits of said 2N bits of information on said memory bus read from said main memory to be written into one of the N bit widths of said instruction buffer and a further N bits of said memory bus being selected to enable a further N bits of said 2N bits of information on said memory bus read from said main memory to be written into the other of the N bit widths of said instruction buffer.

Claim 9

In an information processor according to claim 6, wherein the improvement further comprises said microprogram control section including means for storing said at least one microprogram comprised of microinstructions, means for reading microinstructions from said means for storing and means for holding a microinstruction read from said means for storing, and means for reading N bit information from said instruction buffer to said N bit data bus, said microprogram control section means for reading selecting a start address of a microprogram contained in said means for storing in accordance with an operation code included in the N bit information contained in one of said N bit widths of said instruction buffer and reading the first microinstruction of said selected microprogram to said means for holding.

Claim 10

In an information processor according to claim 7, wherein the improvement further comprises said first means including means for causing N bit information to be read from said main memory into said one N bit width of said instruction buffer while said microinstruction held in said means for holding is being executed.

Claim 11

In an information processor according to claim 7, wherein the improvement further comprises said microprogram control section means for reading including means for reading a subsequent microinstruction of the selected microprogram while said first microinstruction is being executed.

Claim 12

In an information processor according to claim 9, wherein the improvement further comprises said instruction buffer reading means including means for reading N bit information from the other of said N bit width of said instruction buffer to said N bit data bus while said subsequent microinstruction is being executed.