US4070657A
Expired / Lapsed
US
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Current mode simultaneous dual-read/single-write memory device
Assignee: Bull HN Information Systems Inc
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Filing: 1977-01-03
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Granted: 1978-01-24
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Expires: 1997-01-03
Abstract
Abstract A current mode 20-bit memory is organized as four words each containing five bits. The memory comprises a clock circuit a data-in circuit, comprising a plurality of data selectors and master latch registers, a data-out circuit comprising two independent sets of output buffers, two independent read select circuits, a write select circuit, a 4x5 matrix of memory cells, and non-functional testing circuit. In one mode data may be independently read from any two words at the same time that data is written into any one word. In another mode, all bits in a selected word may be synchronously reset. In a third mode the storage elements associated with one selected word may be configured as an inverting shift register for testing and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.
Inventors
- 👤 Darrell LeRoy Fett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/32; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31727; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C11/413; G11C11/414; G11C11/415; G11C29/34; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
444 words
An improved current mode simultaneous dual-read/single-write memory device comprising: a plurality of n data-in circuits, each data-in circuit comprising a data selector circuit and a master latch register, each of said master latch registers generating a true data-in signal and a complement data-in signal, a write select circuit responsive to a plurality of write select signals for generating one of m write select commands over m write select lines, first and second read select circuits, said first read select circuit being responsive to a plurality of first read select signals for generating one of m first read select command signals, and said second read select circuit being responsive to a plurality of second read select signals for generating one of m second read select command signals, a control circuit responsive to a clock signal $ and to a clock enable signal ¢$, said control circuit generating an output signal to each of said master latch registers and to said write select circuit, an m×n matrix of memory cells, where m represents the number of words to be stored in said memory cells and n represents the number of bits per word, each cell comprising first and second dual emitter bipolar transistors, the base of each transistor being connected to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, one emitter of each transistor being connected to one of m write select lines, the remaining emitter of said first transistor being connected to said complement data-in signal of one of said master latch registers, the remaining emitter of said second transistor being connected to the true data-in signal of said master latch register, a first memory cell read enable circuit, said first memory cell read enable circuit responsive to said first read select command signal and being capable of distinguishing between conduction or non-conduction in said first and second transistors, said first memory cell read enable circuit generating a first true readout signal and a first complement readout signal, a second memory cell read enable circuit responsive to said second read select command signal and being capable of distinguishing between conduction or non-conduction in said first and second transistors, said second memory cell read enable circuit generating a second true readout signal and a second complement readout signal, first and second sets of n data output buffers, said first set of n buffers being responsive to said first true and complement readout signals from said first memory cell read enable circuit and said second set of n buffers being responsive to said second true and complement readout signals from said second memory cell read enable circuit.
Claim 2
Dependent Claim
444 words
An improved current mode simultaneous dual-read/single-write memory device comprising: a plurality of n data-in circuits, each data-in circuit comprising a data selector circuit and a master latch register, each of said master latch registers generating a true data-in signal and a complement data-in signal, a write select circuit responsive to a plurality of write select signals for generating one of m write select commands over m write select lines, first and second read select circuits, said first read select circuit being responsive to a plurality of first read select signals for generating one of m first read select command signals, and said second read select circuit being responsive to a plurality of second read select signals for generating one of m second read select command signals, a control circuit responsive to a clock signal $ and to a clock enable signal ¢$, said control circuit generating an output signal to each of said master latch registers and to said write select circuit, an m×n matrix of memory cells, where m represents the number of words to be stored in said memory cells and n represents the number of bits per word, each cell comprising first and second dual emitter bipolar transistors, the base of each transistor being connected to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, one emitter of each transistor being connected to one of m write select lines, the remaining emitter of said first transistor being connected to said complement data-in signal of one of said master latch registers, the remaining emitter of said second transistor being connected to the true data-in signal of said master latch register, a first memory cell read enable circuit, said first memory cell read enable circuit responsive to said first read select command signal and being capable of distinguishing between conduction or non-conduction in said first and second transistors, said first memory cell read enable circuit generating a first true readout signal and a first complement readout signal, a second memory cell read enable circuit responsive to said second read select command signal and being capable of distinguishing between conduction or non-conduction in said first and second transistors, said second memory cell read enable circuit generating a second true readout signal and a second complement readout signal, first and second sets of n data output buffers, said first set of n buffers being responsive to said first true and complement readout signals from said first memory cell read enable circuit and said second set of n buffers being responsive to said second true and complement readout signals from said second memory cell read enable circuit.
Claim 3
Dependent Claim
189 words
The improved current mode simultaneous dual-read/single-write memory device recited in claim 1 wherein said control circuit is further responsive to a non-functional test set signal NFTS and to a non-functional test reset signal NFTR, and wherein each of said data selector circuits comprises: a two-input differential upper level gate, a single input differential upper level gate, and a differential lower level gate, said two-input differential upper level gate receiving as one input a respective one of said n bits of a data word to be written into said memory and receiving as the other input the inverse of said NFTR signal, the outputs of said two-input differential upper level gate being connected to the outputs of said single input differential upper level gate, said input to said single input differential upper level gate being responsive to an NFTIN signal, said differential lower level gate being responsive to said NFTS signal, the non-inverting output from said first differential lower level gate being connected to said single input differential upper level gate, and the inverting output of said differential lower level gate being connected to said two-input differential upper level gate.
Claim 4
Dependent Claim
269 words
The improved current mode simultaneous dual-read/single-write memory device recited in claim 2, wherein each of said master latch registers comprises a first differential upper level gate, a second differential upper level gate, and a differential lower gate, the input to said first differential upper level gate being responsive to the output from said single input differential upper level gate of said data selector circuit, the output of said first differential upper level gate being connected to the input of said second differential upper level gate, the output of said second differential upper level gate being connected to the input thereto, the non-inverting output of said differential lower level gate being connected to said first differential upper level gate, and the inverting output of said differential lower level gate being connected to said second differential upper level gate, and wherein each of said data-in circuits further comprises first and second NAND gates, one input to said first NAND gate being connected to the non-inverting output of said second differential upper level gate, and one input to said second NAND gate being responsive to the inverting output of said second differential upper level gate, the other input to each of said NAND gates being responsive to the output of said control circuit, first and second current switching means, said first current switching means being responsive to the output of said first NAND gate and to a current source for generating said complement data-in signal, and said second current switching means being responsive to the output of said second NAND gates and to a current source for generating said true data-in signal.
Claim 5
Dependent Claim
58 words
The improved current mode simultaneous dual-read/single-write memory device recited in claim 1 wherein each of said output buffers comprises a first and a second emitter follower connected to said true and complement readout signals, respectively, and wherein said memory device further comprises a single output differential buffer connected to the outputs of said first and second emitter followers.
References Cited (Backward Citations)
US3895360A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-23 | 1981-07-25 | 1982-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-23 | 1985-07-25 | 1986-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-23 | 1989-07-25 | 1990-01-24 | $7700.00 | Window Closed / Lapsed |