Patent US5426327A successfully refreshed from Google Patents.
US5426327A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations
Assignee: United Microelectronics Corp
•
Filing: 1993-09-08
•
Granted: 1995-06-20
•
Expires: 2013-09-08
Abstract
Abstract A MOS-type semiconductor device having an LDD structure. The device includes a silicon substrate of a first conductivity type. An insulating film is formed on a main surface of the silicon substrate. A gate electrode made of polycrystalline silicon containing impurities at a first concentration is formed on the insulating film. Sidewall spacers made of polycrystalline silicon containing impurities at a second concentration different from the first concentration are formed at both sides of the gate electrode. Impurity diffusion layers are formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS-type semiconductor device are to be formed. Each of the impurity diffusion layers includes a low concentration diffusion layer disposed at a first portion of one of the regions and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region. The first portion extends between a first end substantially corresponding to a side of the gate electrode contiguous with one of the sidewall spacers and a second end substantially corresponding to an outer side of the one sidewall spacer remote from the side of the gate electrode so that a boundary line between the first portion and the second portion is substantially aligned with the outer side of the one sidewall spacer.
Inventors
- 👤 Ichiro Murai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01322; H10D64/60; H10D64/66; H10D64/671
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
213 words
An MOS type semiconductor device having an LDD structure comprising: a silicon substrate of a first conductivity type; an insulating film formed on a main surface of said silicon substrate; a gate electrode made of polycrystalline silicon containing impurities at a first concentration and formed on said insulating film; sidewall spacers made of polycrystalline silicon containing impurities at a second concentration lower than said first concentration and formed at both sides of the gate electrode; impurity diffusion layers formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS type semiconductor device are to be formed such that the source and drain are spaced from each other with the gate electrode disposed between them, each of the impurity diffusion layers including a low concentration diffusion layer disposed at a first portion of one of the regions just below one of the sidewall spacers and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region; and wherein each of said sidewall spacers is made of a polycrystalline silicon film of the first conductivity type and said gate electrode is made of a polycrystalline silicon film of a second conductivity type different from the first conductivity type.
Claim 2
Dependent Claim
213 words
An MOS type semiconductor device having an LDD structure comprising: a silicon substrate of a first conductivity type; an insulating film formed on a main surface of said silicon substrate; a gate electrode made of polycrystalline silicon containing impurities at a first concentration and formed on said insulating film; sidewall spacers made of polycrystalline silicon containing impurities at a second concentration lower than said first concentration and formed at both sides of the gate electrode; impurity diffusion layers formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS type semiconductor device are to be formed such that the source and drain are spaced from each other with the gate electrode disposed between them, each of the impurity diffusion layers including a low concentration diffusion layer disposed at a first portion of one of the regions just below one of the sidewall spacers and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region; and wherein each of said sidewall spacers is made of a polycrystalline silicon film of the first conductivity type and said gate electrode is made of a polycrystalline silicon film of a second conductivity type different from the first conductivity type.
Claim 3
Dependent Claim
22 words
A MOS type semiconductor device according to claim 1, wherein said second concentration is about 1/10 to 1/100 of said first concentration.
Claim 4
Dependent Claim
235 words
An MOS type semiconductor device having an LDD structure comprising: a silicon substrate of a first conductivity type; an insulating film formed on a main surface of said silicon substrate; a gate electrode made of polycrystalline silicon containing impurities at a first concentration and formed on said insulating film; sidewall spacers made of polycrystalline silicon containing impurities at a second concentration different from said first concentration and formed at both sides of the gate electrode; impurity diffusion layers formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS type semiconductor device are to be formed such that the source and drain are spaced from each other with the gate electrode disposed between them, each of the impurity diffusion layers including a low concentration diffusion layer disposed at a first portion of one of the regions just below one of the sidewall spacers and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region; wherein said second concentration is lower than said first concentration and within a range of about 1/10 to 1/100 of said first concentration; and wherein said sidewall spacers are made of a polycrystalline silicon film of the first conductivity type and said gate electrode is mainly made of a polycrystalline silicon film of a second conductivity type different from the first conductivity type.
Claim 5
Dependent Claim
235 words
An MOS type semiconductor device having an LDD structure comprising: a silicon substrate of a first conductivity type; an insulating film formed on a main surface of said silicon substrate; a gate electrode made of polycrystalline silicon containing impurities at a first concentration and formed on said insulating film; sidewall spacers made of polycrystalline silicon containing impurities at a second concentration different from said first concentration and formed at both sides of the gate electrode; impurity diffusion layers formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS type semiconductor device are to be formed such that the source and drain are spaced from each other with the gate electrode disposed between them, each of the impurity diffusion layers including a low concentration diffusion layer disposed at a first portion of one of the regions just below one of the sidewall spacers and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region; wherein said second concentration is lower than said first concentration and within a range of about 1/10 to 1/100 of said first concentration; and wherein said sidewall spacers are made of a polycrystalline silicon film of the first conductivity type and said gate electrode is mainly made of a polycrystalline silicon film of a second conductivity type different from the first conductivity type.
References Cited (Backward Citations)
US4727038A
Cited
US4971922A
Cited
JPS63122174A
Cited
JPS63168050A
Cited
US4808544A
Cited
JPS6489461A
Cited
US5061975A
Cited
JPH01232765A
Cited
US4868617A
Cited
JPH01278073A
Cited
JPH0234936A
Cited
US5031008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |