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US5424988A
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Stress test for memory arrays in integrated circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1992-09-30
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Granted: 1995-06-13
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Expires: 2012-09-30
Abstract
Abstract A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.
Inventors
- 👤 David C. McClure
- 👤 James Brady
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:18
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/50; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
166 words
A method for testing an array of memory cells in an integrated circuit, each said cell being connected to a complementary pair of bitlines, comprising the steps of: a.) selecting a plurality of row lines simultaneously, such that multiple rows of said array of memory cells are selected; and b.) applying a stress voltage, which is never applied under normal operating conditions, to a plurality of said bitlines of the array of memory cells for a predetermined time period, without simultaneously applying the stress voltage to bitlines of the same complementary pair; and wherein step b) further comprises the steps of i.) setting a plurality of first bit lines of said array to an overvoltage level, which is greater than any normal operating voltage of said array, for a predetermined time period; and ii.) setting a plurality of second bit lines of said array, which are each complementary to a respective one of said first bit lines, to the overvoltage level for a predetermined time period.
Claim 2
Independent Claim
166 words
A method for testing an array of memory cells in an integrated circuit, each said cell being connected to a complementary pair of bitlines, comprising the steps of: a.) selecting a plurality of row lines simultaneously, such that multiple rows of said array of memory cells are selected; and b.) applying a stress voltage, which is never applied under normal operating conditions, to a plurality of said bitlines of the array of memory cells for a predetermined time period, without simultaneously applying the stress voltage to bitlines of the same complementary pair; and wherein step b) further comprises the steps of i.) setting a plurality of first bit lines of said array to an overvoltage level, which is greater than any normal operating voltage of said array, for a predetermined time period; and ii.) setting a plurality of second bit lines of said array, which are each complementary to a respective one of said first bit lines, to the overvoltage level for a predetermined time period.
Claim 3
Dependent Claim
56 words
The method of claim 1, further comprising the steps of: setting the plurality of second bit lines to a low voltage while said first bit lines are each set to said overvoltage level; and setting the plurality of first bit lines to a low voltage while said second bit lines are set to said overvoltage level.
Claim 4
Dependent Claim
52 words
The method of claim 1, further comprising the steps of: letting the plurality of second bit lines float while the plurality of bit lines are set to said overvoltage level; and letting the plurality of first bit lines float while the plurality of second bit lines are set to said overvoltage level.
Claim 5
Dependent Claim
30 words
The method of claim 1, wherein said step of selecting the plurality of row lines simultaneously comprises selecting all of the row lines in the array of memory cells simultaneously.
Claim 6
Dependent Claim
30 words
The method of claim 1, wherein the selected plurality of row lines is less than all of the row lines in the array of memory cells in the integrated circuit.
Claim 7
Dependent Claim
22 words
The method of claim 5, wherein said stress voltage is applied to only a selected portion of the array of memory cells.
Claim 8
Dependent Claim
20 words
The method of claim 1, wherein said predetermined time period extends for the entire duration of stress testing said array.
Claim 9
Dependent Claim
51 words
The method of claim 1, wherein said step of setting the plurality of first bit lines to the overvoltage level for the predetermined time period comprises setting a portion of the bit lines in the array of memory cells to the overvoltage level for the duration of a testing time period.
Claim 10
Dependent Claim
46 words
The method of claim 1, wherein said step of setting the plurality of second bit lines to the overvoltage voltage level for the predetermined time period comprises setting all of the second bit lines to the overvoltage level for the duration of a testing time period.
Claim 11
Independent Claim
84 words
A method for testing an array of memory cells, comprising the steps of selecting a plurality of row lines simultaneously for a testing period; setting a plurality of first bit lines to an overvoltage level, which is greater than any normal operating voltage of said array, for a predetermined time period; and setting a plurality of second bit lines of said array, which are each complementary to a respective one of said first bit lines, to the overvoltage level for a predetermined time period.
Claim 12
Independent Claim
84 words
A method for testing an array of memory cells, comprising the steps of selecting a plurality of row lines simultaneously for a testing period; setting a plurality of first bit lines to an overvoltage level, which is greater than any normal operating voltage of said array, for a predetermined time period; and setting a plurality of second bit lines of said array, which are each complementary to a respective one of said first bit lines, to the overvoltage level for a predetermined time period.
Claim 13
Dependent Claim
58 words
The method of claim 10, further comprising the steps of: setting said plurality of second bit lines to a low voltage while the plurality of first bit lines are each set to said overvoltage level; and setting the plurality of first bit lines to a low voltage while said second bit lines are set to the high voltage.
Claim 14
Dependent Claim
45 words
The method of claim 10, further comprising the steps of: letting said second bit lines float while said first bit lines are set to said overvoltage level; and letting said first bit lines float while said second bit lines are set to said overvoltage level.
Claim 15
Dependent Claim
37 words
The method of claim 10, wherein said step of selecting the plurality of row lines simultaneously for the testing period comprises selecting all of the row lines in the array of memory cells for the testing period.
Claim 16
Dependent Claim
29 words
The method of claim 10, wherein the selected plurality of row lines is less than all of row lines in the array of memory cells in the integrated circuit.
Claim 17
Dependent Claim
46 words
The method of claim 10, wherein said step of setting said first bit lines to the overvoltage level for the predetermined time period comprises setting all of the first bit lines in the array of memory cells to the overvoltage level for the predetermined time period.
Claim 18
Dependent Claim
34 words
The method claim 10, wherein said step of setting said second bit lines to the overvoltage level comprises setting all of the second bit lines to the overvoltage level for the predetermined time period.
Claim 19
Independent Claim
129 words
A method for testing an array of memory cells, each said cell being connected to a bit line and a complementary bit line, comprising the steps of: writing data into said array of memory cells, to set one or more of said bit lines to a first voltage, which is greater than any applied under normal operating conditions, and respective one or more of said complementary bit lines to the complement of said first voltage; and while retaining said data in said array of cells, setting one or more of said complementary bit lines to said first voltage and respective one or more of said bit lines to the complement of said first voltage for a predetermined time period; whereby memory cells having leaky pass transistors can be detected.
Claim 20
Independent Claim
129 words
A method for testing an array of memory cells, each said cell being connected to a bit line and a complementary bit line, comprising the steps of: writing data into said array of memory cells, to set one or more of said bit lines to a first voltage, which is greater than any applied under normal operating conditions, and respective one or more of said complementary bit lines to the complement of said first voltage; and while retaining said data in said array of cells, setting one or more of said complementary bit lines to said first voltage and respective one or more of said bit lines to the complement of said first voltage for a predetermined time period; whereby memory cells having leaky pass transistors can be detected.
Claim 21
Dependent Claim
117 words
A memory in an integrated circuit, comprising: a row decoder; a column decoder; a memory array comprising a plurality of memory cells, each of said cells being connected to an associated bitline and an associated complementary biline, wherein said row decoder and said column decoder are utilized to access said memory array; and a control circuit, wherein said control circuit is connected to selectably place the plurality of said memory cells into a test mode such that an overvoltage, which is outside the normal range of operating voltages of said cells, is first applied to said associated bilines and then to said associated complementary bitlines of said memory array in order to stress test the memory array.
Claim 22
Dependent Claim
117 words
A memory in an integrated circuit, comprising: a row decoder; a column decoder; a memory array comprising a plurality of memory cells, each of said cells being connected to an associated bitline and an associated complementary biline, wherein said row decoder and said column decoder are utilized to access said memory array; and a control circuit, wherein said control circuit is connected to selectably place the plurality of said memory cells into a test mode such that an overvoltage, which is outside the normal range of operating voltages of said cells, is first applied to said associated bilines and then to said associated complementary bitlines of said memory array in order to stress test the memory array.
Claim 23
Dependent Claim
24 words
The method of claim 1, wherein said step of applying a voltage stress is performed in response to an input received from a probe.
Claim 24
Dependent Claim
14 words
The method of claim 1, wherein said memory cells consist of static RAM cells.
Claim 25
Dependent Claim
15 words
The method of claim 1, wherein said memory cells consist of 4-transistor static RAM cells.
Claim 26
Dependent Claim
16 words
The method of claim 1, wherein said overvoltage level is in the neighborhood of 7 volts.
Claim 27
Dependent Claim
23 words
The method of claim 10, wherein said steps of applying overvoltage levels are performed in response, to an input received from a probe.
Claim 28
Dependent Claim
14 words
The method of claim 10, wherein said memory cells consist of static RAM cells.
Claim 29
Dependent Claim
15 words
The method of claim 10, wherein said memory cells consist of 4-transistor static RAM cells.
Claim 30
Dependent Claim
16 words
The method of claim 10, wherein said overvoltage level is in the neighborhood of 7 volts.
Claim 31
Dependent Claim
14 words
The method of claim 10, Wherein said memory cells consist of static RAM cells.
Claim 32
Dependent Claim
15 words
The method of claim 17, wherein said memory cells consist of 4-transistor static RAM cells.
Claim 33
Dependent Claim
14 words
The method of claim 17, wherein said memory cells consist of static RAM cells.
Claim 34
Dependent Claim
17 words
The method of claim 17, wherein said complementary voltage levels are never applied under normal operating conditions.
Claim 35
Dependent Claim
45 words
The integrated circuit memory of claim 18, wherein said control circuitry forces said address decoder circuitry to access a large number of said memory cells simultaneously only if a predetermined signal is received on a probe pad which is not connected to any bond wire.
Claim 36
Dependent Claim
128 words
A low-power integrated circuit memory, comprising: an array of memory cells, each comprising a latch and each of said cells being connected to a complementary pair of bitlines; address decoder circuitry, connected to access selected ones of said memory cells in accordance with externally received addresses, and additional circuitry connected to provide data input and output to a selected one of said memory cells; control circuitry, connected to force said address decoder circuitry to access a large number of said memory cells simultaneously, and to hold said memory cells in an accessed state while an overvoltage, which is outside the normal range of operating voltages of said cells, is applied to each of said accessed cells, without simultaneously applying the overvoltage to bitlines of the same complementary pair.
Claim 37
Dependent Claim
128 words
A low-power integrated circuit memory, comprising: an array of memory cells, each comprising a latch and each of said cells being connected to a complementary pair of bitlines; address decoder circuitry, connected to access selected ones of said memory cells in accordance with externally received addresses, and additional circuitry connected to provide data input and output to a selected one of said memory cells; control circuitry, connected to force said address decoder circuitry to access a large number of said memory cells simultaneously, and to hold said memory cells in an accessed state while an overvoltage, which is outside the normal range of operating voltages of said cells, is applied to each of said accessed cells, without simultaneously applying the overvoltage to bitlines of the same complementary pair.
Claim 38
Dependent Claim
45 words
The integrated circuit memory of claim 32, wherein said control circuitry forces said address decoder circuitry to access a large number of said memory cells simultaneously only if a predetermined signal is received on a probe pad which is not connected to any bond wire.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-12 | 1998-12-12 | 1999-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-12 | 2002-12-12 | 2003-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-12 | 2006-12-12 | 2007-06-13 | $7700.00 | Window Closed / Lapsed |