US5046049A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of flash write for testing a RAM
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-03-20
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Granted: 1991-09-03
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Expires: 2010-03-20
Abstract
Abstract In a memory device(DRAM), an improved flash write test method is disclosed whereby all the memory cells in a memory cell array of a memory device can be written with the internally same data or the externally same data. The bit lines are arranged such that the bit lines B/L and B/L are alternating throughout the memory cell array and such that one word line is connected to only one type(either B/L or B/L) of bit lines, and the data supply circuit is formed by a data controller which controls input/output drives according to the type of the bit lines connected to the selected word line.
Inventors
- 👤 Hoon Choi
- 👤 Seo Dong-Il
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:44
CPC Classifications
G; G11; G11C; G11C29/00; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4072; G11C11/409; G11C11/4096; G11C11/4097; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/36
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
177 words
A flash write method for testing RAM's in a RAM device including a transfer means for transferring row address signals to a memory cell array, said transfer means including a row address buffer and a row decoder, a data supply means for supplying data to be written into each cell of the memory cell array, said data supply means having input/output drivers and a data supply block, a memory cell array having memory areas such as first memory area and second memory area, said memory areas each comprising sense amplifiers and memory cells, and a gate means for connecting the first and second memory areas of the memory cell array with the data supply means, said gate means being inserted between the bit lines (B/L and B/L) and the input lines (I/O and I/O), which comprises arranging the pair of bit lines (B/L and B/L) in an alternating manner wherein the relative positions of the pair of bit lines (B/L and B/L) in the first and second memory areas are the same throughout the memory cell array.
Claim 2
Dependent Claim
177 words
A flash write method for testing RAM's in a RAM device including a transfer means for transferring row address signals to a memory cell array, said transfer means including a row address buffer and a row decoder, a data supply means for supplying data to be written into each cell of the memory cell array, said data supply means having input/output drivers and a data supply block, a memory cell array having memory areas such as first memory area and second memory area, said memory areas each comprising sense amplifiers and memory cells, and a gate means for connecting the first and second memory areas of the memory cell array with the data supply means, said gate means being inserted between the bit lines (B/L and B/L) and the input lines (I/O and I/O), which comprises arranging the pair of bit lines (B/L and B/L) in an alternating manner wherein the relative positions of the pair of bit lines (B/L and B/L) in the first and second memory areas are the same throughout the memory cell array.
Claim 3
Dependent Claim
65 words
A flash write method for testing RAM's according to claim 1, wherein the data supply means forming the data supply block comprises a data controller controlled by a row address buffer, and one of the plurality of row address signals from the row address buffer is supplied to the input/output drivers and as a control signal wherein data pattern is supplied to a memory cell.
References Cited (Backward Citations)
US4703453A
Cited
US4661930A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |