US5423014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Instruction fetch unit with early instruction fetch mechanism
Assignee: Intel Corp
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Filing: 1994-02-24
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Granted: 1995-06-06
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Expires: 2014-02-24
Abstract
Abstract An instruction fetch unit in which an early instruction fetch is initiated to access a main memory simultaneously with checking a cache for the desired instruction. On a slow path to main memory is a large main translation lookaside buffer (TLB) that holds address translations. On a fast path is a smaller translation write buffer (TWB), a mini-TLB, that holds recently used address translations. A guess fetch access in initiated by presenting an address to the main memory in parallel with presenting the address to the cache. The address is compared with the contents of the TWB for a hit and with the contents of the cache for a hit. The guess access is allowed to proceed upon the condition that there is a hit in the TWB (the TWB is able to translate the logical address into a physical address) and a miss in the I-cache (the data are not available in the I-cache and hence the guess access of main memory is necessary to get the data). The guess access is canceled upon the condition that there is either a miss in the TWB (the TWB is unable to translate the logical address into a physical address) or a hit in the I-cache (the data are available in the I-cache and hence the guess access of main memory is not necessary). In this case a fetch access is reissued on the "slow" path that goes through the large main TLB.
Inventors
- 👤 Glenn J. Hinton
- 👤 Robert M. Riches, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F2212/00; G06F2212/68; G06F2212/681
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
In a data processing system, that includes a bus controller for accessing a main memory; an instruction fetch unit (IFU) which has therein instruction fetch logic and a translation write buffer (TWB); a cache having a cache contents for storing instructions at physical addresses and for fetching instructions from said bus controller; said TWB being a small translator having a TWB contents for mapping at least two logical addresses to physical addresses of said cache; a method of fetching instructions in response to a logical address in an instruction pointer comprising the steps of: A. asserting an early fetch line to said bus controller; B. presenting a logical address from said IFU to said TWB; C. Checking said logical address with said TWB contents of said TWB for a hit; D. Checking a physical address translated from said logical address with said cache contents of said cache for a hit; and, E. asserting a cancel early fetch line to said bus controller upon a second condition that there is either a miss in said TWB or a hit in said cache.
Claim 2
Dependent Claim
181 words
In a data processing system, that includes a bus controller for accessing a main memory; an instruction fetch unit (IFU) which has therein instruction fetch logic and a translation write buffer (TWB); a cache having a cache contents for storing instructions at physical addresses and for fetching instructions from said bus controller; said TWB being a small translator having a TWB contents for mapping at least two logical addresses to physical addresses of said cache; a method of fetching instructions in response to a logical address in an instruction pointer comprising the steps of: A. asserting an early fetch line to said bus controller; B. presenting a logical address from said IFU to said TWB; C. Checking said logical address with said TWB contents of said TWB for a hit; D. Checking a physical address translated from said logical address with said cache contents of said cache for a hit; and, E. asserting a cancel early fetch line to said bus controller upon a second condition that there is either a miss in said TWB or a hit in said cache.
Claim 3
Dependent Claim
67 words
The method in accordance with claim 1 wherein said data processing system further includes a main translation lookaside buffer (TLB), said TLB being a large translator for mapping more than two logical addresses to physical addresses of said main memory, said method further comprising the steps of: F. issuing a fetch access to said TLB upon a third condition that there is a miss in said TWB.
Claim 4
Dependent Claim
256 words
In a data processing system, that includes a bus controller for accessing a main memory; an instruction fetch unit (IFU) which has therein a translation write buffer (TWB); a cache connected to said TWB and to said bus controller for storing instructions at physical addresses and for receiving instructions fetched by said bus controller; said TWB being a small translator having a TWB contents for mapping at least two logical addresses to physical addresses of said cache; an apparatus for fetching instructions in response to a logical address in an instruction pointer comprising: control logic means connected to said TWB and to said bus controller; said control logic including an early fetch line connected to said bus controller; said control logic including means for asserting said early fetch line; said control logic including means for presenting a logical address to said TWB; said control logic including a cancel early fetch line connected to said bus controller; said TWB including TWB comparing means for checking said logical address with said TWB contents of said TWB for a hit; said cache including cache comparing means connected to said control logic means for comparing said physical address with said cache contents of said cache for a hit; said control logic means including canceling means for asserting said cancel early fetch line upon a condition that there is either a miss in said TWB or a hit in said cache; said bus controller including means responsive to said cancel early fetch line for canceling said access to said main memory.
Claim 5
Dependent Claim
256 words
In a data processing system, that includes a bus controller for accessing a main memory; an instruction fetch unit (IFU) which has therein a translation write buffer (TWB); a cache connected to said TWB and to said bus controller for storing instructions at physical addresses and for receiving instructions fetched by said bus controller; said TWB being a small translator having a TWB contents for mapping at least two logical addresses to physical addresses of said cache; an apparatus for fetching instructions in response to a logical address in an instruction pointer comprising: control logic means connected to said TWB and to said bus controller; said control logic including an early fetch line connected to said bus controller; said control logic including means for asserting said early fetch line; said control logic including means for presenting a logical address to said TWB; said control logic including a cancel early fetch line connected to said bus controller; said TWB including TWB comparing means for checking said logical address with said TWB contents of said TWB for a hit; said cache including cache comparing means connected to said control logic means for comparing said physical address with said cache contents of said cache for a hit; said control logic means including canceling means for asserting said cancel early fetch line upon a condition that there is either a miss in said TWB or a hit in said cache; said bus controller including means responsive to said cancel early fetch line for canceling said access to said main memory.
Claim 6
Dependent Claim
23 words
The apparatus in accordance with claim 1 wherein said control logic means further includes issue fetch means for reissuing said guess fetch access.
Claim 7
Dependent Claim
252 words
In a data processing system, that includes a main memory, a combination comprising: a bus controller for initiating an access to said main memory; an instruction fetch unit (IFU); said IFU including a translation write buffer (TWB); a cache connected to said TWB and to said bus controller; said cache including means for receiving instructions fetched by said bus controller; said cache including means for storing said instructions at physical addresses; said TWB being a small translator having a TWB contents for mapping at least two logical addresses to physical addresses of said cache; control logic connected to said TWB and to said bus controller; said control logic including an early fetch line connected to said bus controller; said control logic including means for asserting said early fetch line; said control logic including means for presenting a logical address; said control logic including a cancel early fetch line connected to said bus controller; said TWB including TWB comparing means for checking said logical address with said TWB contents of said TWB for a hit; said cache including cache comparing means connected to said control logic means for comparing said logical address with said cache contents of said cache for a hit; said control logic including canceling means for asserting said cancel early fetch line upon a condition that there is either a miss in said TWB or a hit in said cache; said bus controller including means responsive to said cancel early fetch line for canceling said access to said main memory.
Claim 8
Dependent Claim
252 words
In a data processing system, that includes a main memory, a combination comprising: a bus controller for initiating an access to said main memory; an instruction fetch unit (IFU); said IFU including a translation write buffer (TWB); a cache connected to said TWB and to said bus controller; said cache including means for receiving instructions fetched by said bus controller; said cache including means for storing said instructions at physical addresses; said TWB being a small translator having a TWB contents for mapping at least two logical addresses to physical addresses of said cache; control logic connected to said TWB and to said bus controller; said control logic including an early fetch line connected to said bus controller; said control logic including means for asserting said early fetch line; said control logic including means for presenting a logical address; said control logic including a cancel early fetch line connected to said bus controller; said TWB including TWB comparing means for checking said logical address with said TWB contents of said TWB for a hit; said cache including cache comparing means connected to said control logic means for comparing said logical address with said cache contents of said cache for a hit; said control logic including canceling means for asserting said cancel early fetch line upon a condition that there is either a miss in said TWB or a hit in said cache; said bus controller including means responsive to said cancel early fetch line for canceling said access to said main memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-05 | 1998-12-05 | 1999-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-05 | 2002-12-05 | 2003-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-05 | 2006-12-05 | 2007-06-06 | $7700.00 | Window Closed / Lapsed |