Dynamic disable mechanism for a memory management unit

Claim 1

A data processing system, comprising: a memory for storing a plurality of instructions at respective physical addresses; a processor for executing the instructions, the processor requesting the instructions using logical addresses; means coupled to the memory and processor for external monitoring, by a user, of processing activities of the system; a memory management unit (MMU) for selectively translating the logical addresses to respective physical addresses, said MMU being selectively disabled by the processor to inhibit said translating wherein said MMU outputs logical addresses as physical addresses; the improvement comprising: MMU address translation disable means provided in the MMU, said address translation disable means disabling the MMU from performing address translations in response to either a translation enable signal originating from the processor or in response to a dynamic disable signal provided by the means for monitoring; and control means provided in the MMU and coupled to the processor and memory, said control means selectively reading translation information required by the MMU, but not resident in the MMU, and residing in the memory, and replacing predetermined translation information in the MMU with the required translation information.