Simplified contact method for high density CMOS

Claim 1

A method of forming an LDD transistor in a silicon layer comprising the steps of: preparing a silicon substrate; forming a gate stack comprising a gate oxide, a gate electrode layer having a gate top surface and a first sacrificial dielectric; patterning said gate stack to define a gate stack column having vertical sidewalls and source and drain regions in said silicon layer adjoining said gate stack column; oxidizing said vertical sidewalls; depositing a conformal etch resistant dielectric over said gate stack column and said source and drain areas; depositing a second sacrificial dielectric over said conformal dielectric in said gate stack column and said source and drain areas; directionally etching horizontal portions of said second sacrificial dielectric and said conformal dielectric, thereby exposing said first sacrificial dielectric and said source and drain areas and leaving first gate sidewalls including at least said conformal dielectric; removing said first sacrificial dielectric, leaving vertical alignment stubs of said conformal dielectric adjacent extending from said first gate sidewalls above said gate top surface; depositing a protective conformal dielectric having a nominal contact cover thickness above said gate stack column, thereby forming self-aligned protective members about each of said vertical alignment stubs and having a thickness greater than said nominal contact cover thickness; depositing a first interlayer dielectric; etching contact holes above said source and drain regions through said interlayer dielectric and through said protective conformal dielectric to said source and drain regions, whereby a residual thickness of said protective conformal dielectric remains above corners of said gate stack column; and completing said integrated circuit.

Claim 2

A method of forming an LDD transistor in a silicon layer comprising the steps of: preparing a silicon substrate; forming a gate stack comprising a gate oxide, a gate electrode layer having a gate top surface and a first sacrificial dielectric; patterning said gate stack to define a gate stack column having vertical sidewalls and source and drain regions in said silicon layer adjoining said gate stack column; oxidizing said vertical sidewalls; depositing a conformal etch resistant dielectric over said gate stack column and said source and drain areas; depositing a second sacrificial dielectric over said conformal dielectric in said gate stack column and said source and drain areas; directionally etching horizontal portions of said second sacrificial dielectric and said conformal dielectric, thereby exposing said first sacrificial dielectric and said source and drain areas and leaving first gate sidewalls including at least said conformal dielectric; removing said first sacrificial dielectric, leaving vertical alignment stubs of said conformal dielectric adjacent extending from said first gate sidewalls above said gate top surface; depositing a protective conformal dielectric having a nominal contact cover thickness above said gate stack column, thereby forming self-aligned protective members about each of said vertical alignment stubs and having a thickness greater than said nominal contact cover thickness; depositing a first interlayer dielectric; etching contact holes above said source and drain regions through said interlayer dielectric and through said protective conformal dielectric to said source and drain regions, whereby a residual thickness of said protective conformal dielectric remains above corners of said gate stack column; and completing said integrated circuit.