Method for the self-alignment of metal contacts on a semiconductor device, and self-aligned semiconductors

Claim 1

A method for self-alignment of metal electron contacts on a semiconductor device comprising at least one raised pattern on a semiconductor body, said method comprising the following operations: depositing by an isotropic method, on free surfaces of the body and of the pattern, including a lateral surface and flanks of said pattern, of a first insulating layer of silica SiO 2 and then a second insulating layer of silicon nitride Si 3 N 4 with well-controlled thicknesses, anisotropic, reactive ion etching, by SF 6 , of the second layer in its parts deposited on the free surfaces of the body and on top of the pattern, portions of said second layer deposited on the flanks of the pattern remaining unetched, anisotropic, reactive ion etching, by CHF 3 , of the first layer, with the exception of its portions deposited on the flanks of the pattern, which are masked by the corresponding portions of the second layer; selective and isotropic chemical etching, by a buffered solution of HF/NH 4 F/H 2 O, of the first layer, this etching operation creating a sub-etching in the portions of the first layer that are partially masked by the corresponding portions of the second layer not etched by said selective solution, self-aligned metallization, by a directional method, of the metal electrode contacts of the semiconductor device, the juxtaposed portions of the first and second insulating layers on the flanks of the pattern constituting sidewalls between regions of the semiconductor device controlled by two neighboring metallizations.

Claim 2

A method for self-alignment of metal electron contacts on a semiconductor device comprising at least one raised pattern on a semiconductor body, said method comprising the following operations: depositing by an isotropic method, on free surfaces of the body and of the pattern, including a lateral surface and flanks of said pattern, of a first insulating layer of silica SiO 2 and then a second insulating layer of silicon nitride Si 3 N 4 with well-controlled thicknesses, anisotropic, reactive ion etching, by SF 6 , of the second layer in its parts deposited on the free surfaces of the body and on top of the pattern, portions of said second layer deposited on the flanks of the pattern remaining unetched, anisotropic, reactive ion etching, by CHF 3 , of the first layer, with the exception of its portions deposited on the flanks of the pattern, which are masked by the corresponding portions of the second layer; selective and isotropic chemical etching, by a buffered solution of HF/NH 4 F/H 2 O, of the first layer, this etching operation creating a sub-etching in the portions of the first layer that are partially masked by the corresponding portions of the second layer not etched by said selective solution, self-aligned metallization, by a directional method, of the metal electrode contacts of the semiconductor device, the juxtaposed portions of the first and second insulating layers on the flanks of the pattern constituting sidewalls between regions of the semiconductor device controlled by two neighboring metallizations.

Claim 5

A method for self-alignment of metal electrode contacts on a semiconductor device wherein one of said contacts is a Schottky type gate and said semiconductor device includes at least one raised pattern on a semiconductor body, said method comprising the steps of: metaling said Schottky type gate contact; depositing by an isotropic method, on free surfaces of the body and of the pattern, including a lateral surface and flanks of said pattern, of a first insulating layer of silica SiO 2 and subsequently a second insulating layer of silicon nitride Si 3 N 4 with well-controlled thicknesses; anisotropic, reactive ion etching, by SF 6 , of the second layer and its parts deposited on the free surfaces of the body and on top of the pattern, portions of said layer deposited on the flanks of the pattern remaining unetched; anisotropic, reactive ion etching, by CHF 3 ,f of the first layer, with the exception of its portion deposited on the flanks of the pattern, which are masked by the corresponding portions of the second layer; selective and isotropic chemical etching, by buffered solution of HF/NH 4 F/H 2 O, of the first layer, said etching operation creating a sub-etching in the portions of the first layer that are partially masked by the corresponding portions of the second layer not etched by said selective solution; self-aligned metallization, by a directional method, of the metal electrode contacts not including said Schottky type contact, of the semiconductor device, the juxtaposed portions of the first and second insulating layers on the flanks of the pattern constituting side walls between regions of the semiconductor device controlled by two neighboring metallizations.

Claim 6

A method for self-alignment of metal electrode contacts on a semiconductor device wherein one of said contacts is a Schottky type gate and said semiconductor device includes at least one raised pattern on a semiconductor body, said method comprising the steps of: metaling said Schottky type gate contact; depositing by an isotropic method, on free surfaces of the body and of the pattern, including a lateral surface and flanks of said pattern, of a first insulating layer of silica SiO 2 and subsequently a second insulating layer of silicon nitride Si 3 N 4 with well-controlled thicknesses; anisotropic, reactive ion etching, by SF 6 , of the second layer and its parts deposited on the free surfaces of the body and on top of the pattern, portions of said layer deposited on the flanks of the pattern remaining unetched; anisotropic, reactive ion etching, by CHF 3 ,f of the first layer, with the exception of its portion deposited on the flanks of the pattern, which are masked by the corresponding portions of the second layer; selective and isotropic chemical etching, by buffered solution of HF/NH 4 F/H 2 O, of the first layer, said etching operation creating a sub-etching in the portions of the first layer that are partially masked by the corresponding portions of the second layer not etched by said selective solution; self-aligned metallization, by a directional method, of the metal electrode contacts not including said Schottky type contact, of the semiconductor device, the juxtaposed portions of the first and second insulating layers on the flanks of the pattern constituting side walls between regions of the semiconductor device controlled by two neighboring metallizations.