Method of making resistor with silicon-rich silicide contacts for an integrated circuit

Claim 1

A method for fabricating a high impedance load device in an integrated circuit, comprising the steps of: forming an opening in an insulating layer to expose a first region of a semiconductor device below the insulating layer; forming a region of a refractory metal silicide in the opening; and annealing the integrated circuit until a layer of epitaxial silicon from the refractory metal silicide is grown on the region, wherein the layer of epitaxial silicon separates the first region from the refractory metal silicide, wherein a high impedance load device is formed by the layer of epitaxial silicon.

Claim 2

A method for fabricating a high impedance load device in an integrated circuit, comprising the steps of: forming an opening in an insulating layer to expose a first region of a semiconductor device below the insulating layer; forming a region of a refractory metal silicide in the opening; and annealing the integrated circuit until a layer of epitaxial silicon from the refractory metal silicide is grown on the region, wherein the layer of epitaxial silicon separates the first region from the refractory metal silicide, wherein a high impedance load device is formed by the layer of epitaxial silicon.

Claim 4

A method for fabricating a high impedance load device in an integrated circuit, comprising the steps of: forming an opening in an insulating layer to expose a first region below the insulating layer; forming a region of a refractory metal silicide in the opening; annealing the integrated circuit until a layer of epitaxial silicon from the refractory metal silicide is grown on the region, wherein the layer of epitaxial silicon separates the first region from the refractory metal silicide; and implanting dopant atoms into the layer of epitaxial silicon, wherein the refractory metal silicide is tantalum silicide.

Claim 5

A method for fabricating a high impedance load device in an integrated circuit, comprising the steps of: forming an opening in an insulating layer to expose a first region below the insulating layer; forming a region of a refractory metal silicide in the opening; annealing the integrated circuit until a layer of epitaxial silicon from the refractory metal silicide is grown on the region, wherein the layer of epitaxial silicon separates the first region from the refractory metal silicide; and implanting dopant atoms into the layer of epitaxial silicon, wherein the refractory metal silicide is tantalum silicide.

Claim 13

A method for fabricating a static random access memory in an integrated circuit comprising: forming a pass gate transistor; forming a pull-down transistor, wherein the pull-down transistor shares a source/drain region with the pass gate transistor forming an insulating layer over the two transistors; forming an opening in the insulating layer over the shared source/drain region; forming a region of a refractory metal silicide in the opening; and annealing the integrated device such that an epitaxial silicon layer is grown from the refractory metal silicide between the region of refractory metal silicide and the source/drain region, wherein a high impedance load device is formed in the static random access memory by the epitaxial silicon layer.

Claim 14

A method for fabricating a static random access memory in an integrated circuit comprising: forming a pass gate transistor; forming a pull-down transistor, wherein the pull-down transistor shares a source/drain region with the pass gate transistor forming an insulating layer over the two transistors; forming an opening in the insulating layer over the shared source/drain region; forming a region of a refractory metal silicide in the opening; and annealing the integrated device such that an epitaxial silicon layer is grown from the refractory metal silicide between the region of refractory metal silicide and the source/drain region, wherein a high impedance load device is formed in the static random access memory by the epitaxial silicon layer.

Claim 16

A method for fabricating a static random access memory in an integrated circuit comprising: forming a pass gate transistor; forming a pull-down transistor, wherein the pull-down transistor shares a source/drain region with the pass gate transistor; forming an insulating layer over the two transistors; forming an opening in the insulating layer over the shared source/drain region; forming a region of a refractory metal silicide in the opening; annealing the integrated device such that an epitaxial silicon layer is grown from the refractory metal silicide between the region of refractory metal silicide and the source/drain region; and implanting dopant atoms into the layer of epitaxial silicon, wherein the refractory metal silicide is tantalum silicide.

Claim 17

A method for fabricating a static random access memory in an integrated circuit comprising: forming a pass gate transistor; forming a pull-down transistor, wherein the pull-down transistor shares a source/drain region with the pass gate transistor; forming an insulating layer over the two transistors; forming an opening in the insulating layer over the shared source/drain region; forming a region of a refractory metal silicide in the opening; annealing the integrated device such that an epitaxial silicon layer is grown from the refractory metal silicide between the region of refractory metal silicide and the source/drain region; and implanting dopant atoms into the layer of epitaxial silicon, wherein the refractory metal silicide is tantalum silicide.