Bus control system and method that selectively generate an early address strobe

Claim 2

An improved bus control system for a multi-processor system, said multi-processor system having at least two memory modules, at least two processor modules, a common address bus and a common data bus connecting the memory modules to the processor modules, said control system comprising: a bus control circuit on each of said processor modules, said bus control circuit further comprising: a slot identification mapping circuit that determines a first slot identifier of a first one of the memory modules which contains a first address having data requested by a first data request and that determines a second slot identifier of a second one of the memory modules which contains a second address having data requested by a second data request; a storage register that stores the first slot identifier; a comparator that compares the first slot identifier with the second slot identifier; and a first logic circuit that issues an early address request to the common address bus, if the first slot identifier differs from said second slot identifier.

Claim 3

A bus control system for a multi-processor system, said multi-processor system having multiple processor modules, at least two memory modules, a common address and a common data bus connecting the memory modules to the processor modules, said control system comprising: a slot identification mapping circuit that determines a first slot identifier of a first one of the memory modules which contains a first address having data requested by a first data request and that determines a second slot identifier of a second one of the memory modules which contains a second address having data requested by a second data request; a storage register that stores the first slot identifier; a comparator that compares the first slot identifier with the second slot identifier; a first logic circuit that issues an early address request to said common address bus if the first slot identifier differs from said second slot identifier; and a second logic circuit that disables the issuance of the early address request by any one of the processor modules.

Claim 4

A bus control system for a multi-processor system, said multi-processor system having multiple processor modules, at least two memory modules, a common address and a common data bus connecting the memory modules to the processor modules, said control system comprising: a slot identification mapping circuit that determines a first slot identifier of a first one of the memory modules which contains a first address having data requested by a first data request and that determines a second slot identifier of a second one of the memory modules which contains a second address having data requested by a second data request; a storage register that stores the first slot identifier; a comparator that compares the first slot identifier with the second slot identifier; a first logic circuit that issues an early address request to said common address bus if the first slot identifier differs from said second slot identifier; and a second logic circuit that disables the issuance of the early address request by any one of the processor modules.

Claim 7

An improved multi-processor system comprising: at least two memory modules; at least two processor modules, each of said processor modules comprising a local address bus, a local data bus, and a local control bus; and a common address bus, a common data bus and a common control bus connecting the memory modules to the processor modules, each of said processor modules further comprising: a static random access memory with first and second data input ports and a data output port, wherein said first data input port is connected to said local address bus and said second data input port is connected to said local data bus; a storage register with an input port and an output port, said input port connected to said data output port of said static random access memory; a comparator with first and second input ports and an output, wherein said first input port of said comparator is connected to said output port of said static random access memory and said second input port of said comparator is connected to said output port of said storage register; a first gate with first and second inputs and an output, wherein said first input of said first gate is connected to said output of said comparator and said second input of said first gate is connected to said output port of said static random access memory; and a second gate with first and second inputs and an output, wherein said first input of said second gate is connected to said output of said first gate, said second input of said second gate is connected to a first control signal provided by said common control bus to indicate the availability of said common address bus and said output of said second gate is a second control signal which is sent to said common control bus to indicate that an early address request can be sent to said common address bus.

Claim 8

An improved multi-processor system comprising: at least two memory modules; at least two processor modules, each of said processor modules comprising a local address bus, a local data bus, and a local control bus; and a common address bus, a common data bus and a common control bus connecting the memory modules to the processor modules, each of said processor modules further comprising: a static random access memory with first and second data input ports and a data output port, wherein said first data input port is connected to said local address bus and said second data input port is connected to said local data bus; a storage register with an input port and an output port, said input port connected to said data output port of said static random access memory; a comparator with first and second input ports and an output, wherein said first input port of said comparator is connected to said output port of said static random access memory and said second input port of said comparator is connected to said output port of said storage register; a first gate with first and second inputs and an output, wherein said first input of said first gate is connected to said output of said comparator and said second input of said first gate is connected to said output port of said static random access memory; and a second gate with first and second inputs and an output, wherein said first input of said second gate is connected to said output of said first gate, said second input of said second gate is connected to a first control signal provided by said common control bus to indicate the availability of said common address bus and said output of said second gate is a second control signal which is sent to said common control bus to indicate that an early address request can be sent to said common address bus.

Claim 9

An improved multi-processor system comprising: at least two memory modules; at least two processor modules, each of said processor modules comprising a local address bus, a local data bus, and a local control bus; and a common address bus, a common data bus and a common control bus connecting the memory modules to the processor modules, each of said processor modules further comprising: a static random access memory with first and second data input ports and a data output port, wherein said first data input port is connected to said local address bus and said second data input port is connected to said local data bus; a storage register with an input port and an output port, said input port connected to said data output port of said static random access memory, wherein said output port of said static random access memory is divided into a first set and a second set of data bits, wherein said first set of data bits indicates the memory module which contains data that is addressed by the local address bus and wherein said second set of bits indicates if an early address request is desired; a comparator with first and second input ports and an output, wherein said first input port of said comparator is connected to said output port of said static random access memory and said second input port of said comparator is connected to said output port of said storage register;. a first gate with first and second inputs and an output, wherein said first input of said first gate is connected to said output of said comparator and said second input of said first gate is connected to said output port of said static random access memory; and a second gate with first and second inputs and an output, wherein said first input of said second gate is connected to said output of said first gate, said second input of said second gate is connected to a first control signal provided by said common control bus to indicate the availability of said common address bus and said output of said second gate is a second control signal which is sent to said common control bus to indicate that an early address request can be sent to said common address bus.

Claim 10

An improved multi-processor system comprising: at least two memory modules; at least two processor modules, each of said processor modules comprising a local address bus, a local data bus, and a local control bus; and a common address bus, a common data bus and a common control bus connecting the memory modules to the processor modules, each of said processor modules further comprising: a static random access memory with first and second data input ports and a data output port, wherein said first data input port is connected to said local address bus and said second data input port is connected to said local data bus; a storage register with an input port and an output port, said input port connected to said data output port of said static random access memory, wherein said output port of said static random access memory is divided into a first set and a second set of data bits, wherein said first set of data bits indicates the memory module which contains data that is addressed by the local address bus and wherein said second set of bits indicates if an early address request is desired; a comparator with first and second input ports and an output, wherein said first input port of said comparator is connected to said output port of said static random access memory and said second input port of said comparator is connected to said output port of said storage register;. a first gate with first and second inputs and an output, wherein said first input of said first gate is connected to said output of said comparator and said second input of said first gate is connected to said output port of said static random access memory; and a second gate with first and second inputs and an output, wherein said first input of said second gate is connected to said output of said first gate, said second input of said second gate is connected to a first control signal provided by said common control bus to indicate the availability of said common address bus and said output of said second gate is a second control signal which is sent to said common control bus to indicate that an early address request can be sent to said common address bus.

Claim 11

A bus control system for a computer system having multiple CPU modules and multiple shared resources, said control system comprising: a shared bus for communicating address, data and control signals between said CPU modules and said shared resources; a bus controller on each of said CPU modules for initiating accesses to said shared resources in response to addresses from said CPU modules, said bus controller comprising: a decoder for decoding identifications of shared resources being addressed by addresses on said shared bus; a storage device for storing a first identification of a first shared resource for which an access is in progress; and a comparator for comparing said first identification with a second identification of a second shared resource for which an access is requested, said comparator providing an active output signal when said first identification and said second identification are different, said bus controller initiating an access to said second shared resource prior to completion of said access in progress in response to said active output signal.

Claim 12

A bus control system for a computer system having multiple CPU modules and multiple shared resources, said control system comprising: a shared bus for communicating address, data and control signals between said CPU modules and said shared resources; a bus controller on each of said CPU modules for initiating accesses to said shared resources in response to addresses from said CPU modules, said bus controller comprising: a decoder for decoding identifications of shared resources being addressed by addresses on said shared bus; a storage device for storing a first identification of a first shared resource for which an access is in progress; and a comparator for comparing said first identification with a second identification of a second shared resource for which an access is requested, said comparator providing an active output signal when said first identification and said second identification are different, said bus controller initiating an access to said second shared resource prior to completion of said access in progress in response to said active output signal.

Claim 13

A bus control system for a computer system having multiple CPU modules and multiple shared resources, said control system comprising: a shared bus for communicating address, data and control signals between said CPU modules and said shared resources; a bus controller on each of said CPU modules and said shared bus for initiating accesses to said shared resources in response to addresses from said CPU modules, said bus controller comprising: a decoder for decoding identifications of shared resources being addressed by addresses on said shared bus, wherein said decoder comprises a memory which maps an address from said shared bus to an identification of a shared resource uniquely associated with said address; a storage device for storing a first identification of a first shared resource for which an access is in progress; and a comparator for comparing said first identification with a second identification of a second shared resource for which an access is requested, said comparator providing an active output signal when said first identification and said second identification are different, said bus controller initiating an access to said second shared resource prior to completion of said access in progress in response to said active output signal.

Claim 14

A bus control system for a computer system having multiple CPU modules and multiple shared resources, said control system comprising: a shared bus for communicating address, data and control signals between said CPU modules and said shared resources; a bus controller on each of said CPU modules and said shared bus for initiating accesses to said shared resources in response to addresses from said CPU modules, said bus controller comprising: a decoder for decoding identifications of shared resources being addressed by addresses on said shared bus, wherein said decoder comprises a memory which maps an address from said shared bus to an identification of a shared resource uniquely associated with said address; a storage device for storing a first identification of a first shared resource for which an access is in progress; and a comparator for comparing said first identification with a second identification of a second shared resource for which an access is requested, said comparator providing an active output signal when said first identification and said second identification are different, said bus controller initiating an access to said second shared resource prior to completion of said access in progress in response to said active output signal.