Multiprocessor control system

Claim 2

A multiprocessor control system comprising: at least one main storage unit; a plurality of main storage control units, respectively, operatively connected to said at least one main storage unit, each of said plurality of main storage control units including a priority order determination circuit; a plurality of processing units operatively connected to said main storage control units; a control but connected between said main storage control units, each one of said processing units transmitting a request for access to said at least one main storage unit, the requests from each one of said processing units being transmitted to one of said main storage control units simultaneously, and each one of said processing units transmitting an identical request to all of the other ones of said main storage control units through said control bus, said priority order determination circuits synchronously processing requests; and data, transmitted between each one of said processing units and an arbitrary one of said main storage units, being transmitted only through respective ones of said main storage control units connected to each of said processing units.

Claim 3

A multiprocessor control system according to claim 1, wherein at least one of said processing units comprises a vector processing unit, and said main storage control units comprise vector control units.

Claim 4

A multiprocessor control system according to claim 1, wherein said priority order determination circuit comprises: a plurality of bank conflict checkers for controlling use of said main storage unit and providing outputs; a bus conflict checker for controlling common bus use; and a main priority order control circuit controlling said main storage unit upon receipt of the outputs of said bank conflict checkers and said bus conflict checker.

Claim 5

A multiprocessor control system according to claim 1, wherein said request for access to said main storage unit comprises a valid bit designating a validity of the request, one of a plurality of address bits for said main storage unit to be accessed, one of a plurality of operation code bits designating a type of access operation, and a parity bit for said address bits and said operation code bits.

Claim 6

A multiprocessor control system comprising: main storage control units; processing units connected to respective ones of said main storage control units, and cross-coupled to adjacent ones of said main storage control units; and main storage units cross-coupled to said main storage control units, each of said main storage control units comprising: local request ports connected to said processing units for receiving requests from said processing units connected thereto; remote request ports connected to said processing units of adjacent ones of said main storage control units, for receiving requests from said processing units connected to said adjacent ones of said main storage control units; a priority order determination circuit, connected to said local request ports and said remote request ports, for determining access priority order to said main storage units; address registers connected between said priority order determination circuit and said main storage units; and a control bus connecting said processing units and said remote request ports in adjacent ones of said main storage control units.

Claim 7

A multiprocessor control system comprising: main storage control units; processing units connected to respective ones of said main storage control units, and cross-coupled to adjacent ones of said main storage control units; and main storage units cross-coupled to said main storage control units, each of said main storage control units comprising: local request ports connected to said processing units for receiving requests from said processing units connected thereto; remote request ports connected to said processing units of adjacent ones of said main storage control units, for receiving requests from said processing units connected to said adjacent ones of said main storage control units; a priority order determination circuit, connected to said local request ports and said remote request ports, for determining access priority order to said main storage units; address registers connected between said priority order determination circuit and said main storage units; and a control bus connecting said processing units and said remote request ports in adjacent ones of said main storage control units.

Claim 8

A multiprocessor control system according to claim 5, wherein said priority order determination circuit means comprises: request queues, operatively connected to said local request ports and said remote request ports, for receiving request inputs from said local request ports and said remote request ports; bank conflict checkers, operatively connected to said request queues, for receiving request from said request queues for checking bank busy states; a bus conflict checker, operatively connected to said request queues, for receiving requests from said request queues, for checking bus conflict states; and a main priority order determination circuit connected to said bank conflict checkers, said bus conflict checker and said main storage units, for controlling access request to said main storage units in accordance with said bank conflict checkers and bus conflict checker.

Claim 9

A multiprocessor control system according to claim 6, wherein said request queues include first-in-first-out type register groups.

Claim 10

A multiprocessor control system comprising: a plurality of processing units; a plurality of main storage control units each having at least one of said processing units connected thereto; at least one main storage unit connected to said main storage control units; each of said main storage control units comprising a priority order determination circuit for determining a priority order and receiving an access request from a connected one of said processing units; said priority order determination circuit determining an access priority upon receipt of an access request from said connected one of said processing units in one of said main storage control units and an access request from one of said processing units connected to another one of said main storage control units.

Claim 11

A multiprocessor control system comprising: a plurality of processing units; a plurality of main storage control units each having at least one of said processing units connected thereto; at least one main storage unit connected to said main storage control units; each of said main storage control units comprising a priority order determination circuit for determining a priority order and receiving an access request from a connected one of said processing units; said priority order determination circuit determining an access priority upon receipt of an access request from said connected one of said processing units in one of said main storage control units and an access request from one of said processing units connected to another one of said main storage control units.

Claim 12

A multiprocessor control system according to claim 8, wherein said plurality of priority order determination circuits operate synchronously with each other.

Claim 13

A multiprocessor control system according to claim 8, wherein each of said main storage control units comprise: local request ports connected to said processing units for receiving request from said processing units connected thereto; remote request ports connected to said processing units of adjacent ones of said main storage control units, for receiving requests from said processing units connected to said adjacent ones of said main storage control units; priority order determination circuit means, connected to said local request ports and said remote request ports, for determining access priority order to said main storage units; address registers connected between said priority order determination circuit means and said main storage units; and a control but connecting said processing units and said remote request ports in adjacent ones of said main storage control units.

Claim 14

A multiprocessor control system according to claim 10, wherein said priority order determination circuit means comprises: request queues, operatively connected to said local request ports and said remote request ports, for receiving request inputs from said local request ports and said remote request ports; bank conflict checkers, operatively connected to said request queues, for receiving requests from said request queues for checking bank busy states; a bus conflict checker, operatively connected to said request queues, for receiving request from said request queues, for checking bus conflict states; and a main priority order determination circuit connected to said bank conflict checkers, said bus conflict checker and said main storage units, for controlling access requests to said main storage units in accordance with said bank conflict checkers and bus conflict checker.

Claim 15

A multiprocessor control system according to claim 11, wherein said request queues include first-in-first-out type register groups.

Claim 16

A multiprocessor control system comprising: a plurality of main storage units; a first main storage control unit connected to said main storage units; a second main storage control unit connected to said main storage units; at least one processing unit, connected to said first main storage control unit, for requesting access to said first main storage control unit and for receiving an access result from said first main storage control unit; at least one processing unit connected to said second main storage control unit, for requesting access to said second main storage control unit and for receiving an access result from said second main storage control unit; a first priority order determination circuit, in said first main storage control unit and operatively connected to said second main storage control unit, for receiving an access request from said first main storage control unit, and for determining a priority order of an access upon receipt of the access request from said second main storage control unit; and a second priority order determination circuit, in said second main storage control unit and operatively connected to said first main storage control unit, for receiving an access request from said second main storage control unit, and for determining a priority order of an access upon receipt of the access request from said first main storage control unit.

Claim 17

A multiprocessor control system comprising: a plurality of main storage units; a first main storage control unit connected to said main storage units; a second main storage control unit connected to said main storage units; at least one processing unit, connected to said first main storage control unit, for requesting access to said first main storage control unit and for receiving an access result from said first main storage control unit; at least one processing unit connected to said second main storage control unit, for requesting access to said second main storage control unit and for receiving an access result from said second main storage control unit; a first priority order determination circuit, in said first main storage control unit and operatively connected to said second main storage control unit, for receiving an access request from said first main storage control unit, and for determining a priority order of an access upon receipt of the access request from said second main storage control unit; and a second priority order determination circuit, in said second main storage control unit and operatively connected to said first main storage control unit, for receiving an access request from said second main storage control unit, and for determining a priority order of an access upon receipt of the access request from said first main storage control unit.

Claim 18

A multiprocessor control system according to claim 13, wherein said first priority order determination circuit and said second priority order determination circuit determine a priority order of the access request in synchronization with each other.

Claim 19

A multiprocessor control system according to claim 14, wherein at least one of said processing units comprises a vector processing unit, and said main storage control units comprise vector control units.

Claim 20

A multiprocessor control system according to claim 14, wherein said priority order determination circuit comprises: a plurality of bank conflict checkers, operatively connected to said main storage units, for controlling use of a bank of one of said main storage units; a bus conflict checker for controlling common bus use; and a main priority order control circuit, operatively connected between said plurality of bank conflict checkers and said bus conflict checker, and said main storage units, controlling one of said main storage units upon receipt of the outputs of said bank conflict checkers and said bus conflict checker.

Claim 21

A multiprocessor control system according to claim 14, wherein said request for access to each of said main storage units comprises a valid bit designating a validity of the request, an address bit for said main storage unit to be accessed, an operation code bit designating a type of access operation, and a parity bit for said address bit and said operation code bit.

Claim 22

A multiprocessor control system according to claim 13, wherein at least one of said processing units comprises a vector processing unit, and said main storage control units comprise vector control units.

Claim 23

A multiprocessor control system according to claim 13, wherein said first and second priority order determination circuits each comprise: a plurality of bank conflict checkers, operatively connected to said main storage units, for controlling use of a bank of one of said main storage units; a bus conflict checker for controlling common bus use; and a main priority order control circuit, operatively connected between said plurality of bank conflict checkers and said bus conflict checker, and said main storage units, controlling one of said main storage units upon receipt of outputs from said bank conflict checkers and said bus conflict checker.

Claim 24

A multiprocessor control system according to claim 13, wherein said request for access to each of said main storage units comprises a valid bit designating a validity of the request, an address bit for said main storage unit to be accessed, an operation code bit designating a type of access operation, and a parity bit for said address bit and said operation code bit.

Claim 25

A multiprocessor control system comprising: a plurality of main storage units; a first main storage control unit connected to said main storage units; a second main storage control unit connected to said main storage units; at least one processing unit in a set of first processing units, connected to said first main storage control unit, for requesting access to said first main storage control unit, and for receiving an access result from said first main storage control unit; at least one processing unit in a set of second processing units, connected to said second main storage control unit, for requesting access to said second main storage control unit, and for receiving an access result from said second main storage control unit; a first priority order determination circuit, in said first main storage control unit and operatively connected to said second main storage control unit, for receiving an access request from said first main storage control unit, and for determining a priority order of access upon receipt of the access request from said second main storage control unit; and a second priority order determination circuit, in said second main storage control unit and operatively connected to said first main storage control unit, for receiving an access request from said second main storage control unit, and for determining a priority order of an access upon receipt of the access request from said first main storage control unit, said first priority order determination circuit and said second priority order determination circuit determine a priority order of the access request in synchronization with each other.

Claim 26

A multiprocessor control system comprising: a plurality of main storage units; a first main storage control unit connected to said main storage units; a second main storage control unit connected to said main storage units; at least one processing unit in a set of first processing units, connected to said first main storage control unit, for requesting access to said first main storage control unit, and for receiving an access result from said first main storage control unit; at least one processing unit in a set of second processing units, connected to said second main storage control unit, for requesting access to said second main storage control unit, and for receiving an access result from said second main storage control unit; a first priority order determination circuit, in said first main storage control unit and operatively connected to said second main storage control unit, for receiving an access request from said first main storage control unit, and for determining a priority order of access upon receipt of the access request from said second main storage control unit; and a second priority order determination circuit, in said second main storage control unit and operatively connected to said first main storage control unit, for receiving an access request from said second main storage control unit, and for determining a priority order of an access upon receipt of the access request from said first main storage control unit, said first priority order determination circuit and said second priority order determination circuit determine a priority order of the access request in synchronization with each other.

Claim 27

A multiprocessor control system according to claim 21, wherein at least one of said processing units comprises a vector processing unit, and said main storage control units comprise vector control units.

Claim 28

A multiprocessor control system according to claim 21, wherein said first and second priority order determination circuits each comprise: a plurality of bank conflict checkers, operatively connected to said main storage unit, for controlling use of a bank of each of said main storage units; a bus conflict checker for controlling common bus use; and a main priority order control circuit, operatively connected between said plurality of bank conflict checkers and said bus conflict checker, and said main storage units, controlling each of said main storage units upon receipt of outputs from said bank conflict checkers and said but conflict checker.

Claim 29

A multiprocessor control system according to claim 21, wherein said request for access to each of said main storage units comprises a valid bit designating a validity of the request, an address bit for said main storage unit to be accessed, an operation code bit designating a type of access operation, and a parity bit for said address bit and said operation code bit.

Claim 30

A multiprocessor control system comprising: a plurality of main storage units; a first main storage control unit connected to said main storage units; a second main storage control unit connected to said main storage units; at least one processing unit in a set of first processing units, connected to said first main storage control unit, for requesting access to said first main storage control unit, and for receiving an access result from said first main storage control unit; at least one processing unit in a set of second processing units, connected to said second main storage control unit, for requesting access to said second main storage control unit, and for receiving an access result from said second main storage control unit; a first priority order determination circuit provided in said first main storage control unit; a second priority order determination circuit provided in said second main storage control unit; and a control bus for supplying an access request from said first main storage control unit to said second priority order determination circuit and for supplying an access request from said second main storage control unit to said first priority order determination circuit; said first priority order determination circuit determining an access priority order from the access request from said first main storage control unit and from the access request obtained through said control bus, said second priority order determination circuit determining an access priority order from the access request from said second main storage control unit and from the access request obtained through said control bus, and said first and second priority order determination circuits operating synchronously with each other.

Claim 31

A multiprocessor control system comprising: a plurality of main storage units; a first main storage control unit connected to said main storage units; a second main storage control unit connected to said main storage units; at least one processing unit in a set of first processing units, connected to said first main storage control unit, for requesting access to said first main storage control unit, and for receiving an access result from said first main storage control unit; at least one processing unit in a set of second processing units, connected to said second main storage control unit, for requesting access to said second main storage control unit, and for receiving an access result from said second main storage control unit; a first priority order determination circuit provided in said first main storage control unit; a second priority order determination circuit provided in said second main storage control unit; and a control bus for supplying an access request from said first main storage control unit to said second priority order determination circuit and for supplying an access request from said second main storage control unit to said first priority order determination circuit; said first priority order determination circuit determining an access priority order from the access request from said first main storage control unit and from the access request obtained through said control bus, said second priority order determination circuit determining an access priority order from the access request from said second main storage control unit and from the access request obtained through said control bus, and said first and second priority order determination circuits operating synchronously with each other.

Claim 32

A multiprocessor control system according to claim 25, wherein at least one of said processing units comprises a vector processing unit, and said main storage control units comprise vector control units.

Claim 33

A multiprocessor control system according to claim 25, wherein said first and second priority order determination circuits each comprise: a plurality of bank conflict checkers, operatively connected to said main storage units, for controlling use of a bank fo each of said main storage units; a bus conflict checker for controlling common bus use; and a main priority order control circuit, operatively connected between said plurality of bank conflict checkers and said bus conflict checker, and said main storage units, controlling each of said main storage units upon receipt of outputs from said bank conflict checkers and said bus conflict checker.

Claim 34

A multiprocessor control system according to claim 25, wherein said request for access to each of said main storage units comprises a valid bit designating a validity of the request, an address bit for said main storage 1 units to be accessed, an operation code bit designating a type of access operation, and a priority bit for said address bit and said operation code bit.