Data processor system having improved data throughput in a multiprocessor system

Claim 2

A data processor system comprising a plurality of multiprocessor systems each having a memory control unit, each multiprocessor system being connected to the other multiprocessor systems through the memory control unit of each multiprocessor system, each said multiprocessor system comprising: a memory control unit operatively connected to the other multiprocessor systems for data transmission therebetween; at least one central processing unit operatively connected to said memory control unit; and at least one main memory unit operatively connected to said memory control unit and synchronously operated with said memory control unit and each central processing unit.

Claim 3

A data processor system as claimed in claim 1, wherein each said central processing unit sends access request signals and each said memory control unit includes: a first pipeline for controlling access request signals for the main memory unit connected to said memory control unit; a second pipeline for controlling access request signals for another main memory unit connected to another memory control unit; a first access selecting circuit for selecting an access request signal from access request signals from each central processing unit associated with said first access selecting circuit and from other multiprocessor systems to determine whether it is an access request to the main memory unit associated with said first access selecting circuit or another main memory unit associated with another memory control unit, sending the request to the first pipeline of the memory control unit associated with said first access selecting circuit, and duplicating and sending the request to the second pipeline of said another memory control unit; and a second access selecting circuit for selecting an access request signal from access request signals from each central processing unit associated with said second access selecting circuit and sending said request to another main memory unit associated with another memory control unit via the first access selecting circuit of said another memory control unit.

Claim 4

A data processor system as claimed in claim 2, wherein a number of said second pipelines provided is one less than the number of memory control units.

Claim 5

A data processor system as claimed in claim 2, wherein a number of said second access selecting circuits are provided which is the same number as the number of memory control units and each is associated with one of the memory control units.

Claim 6

A multiprocessor system as claimed in claim 2, wherein a number of said first access selecting circuits are provided which is the same number as the number of main memory units associated with the memory control unit and which are associated with each main memory unit.

Claim 7

A multiprocessor system as claimed in claim 2, wherein said memory control unit further includes an address converter for converting a real address generated by said central processing unit to a physical address and is connected to said central processing unit at a stage prior to said first and second access selecting circuits.

Claim 8

A multiprocessor system as claimed in claim 2, wherein said memory control unit further comprises a discriminating circuit for discriminating access request signals for synchronous data transmission to another multiprocessor system.

Claim 11

A method as claimed in claim 8, wherein said memory control unit operates synchronously with the second memory control unit.

Claim 12

A processing system, comprising: a first multiprocessor system comprising a first processing unit, a first memory control unit operatively connected to said first processing unit and a first memory unit operatively connected to said first memory control unit; a second multiprocessor system comprising a second processing unit, a second memory control unit operatively connected to said second processing unit and said first memory control unit, and a second memory unit operatively connected to said second memory control unit; said first memory control unit comprising: first selecting and transmitting means, operatively connected to said first processing unit and said second memory control unit, for selecting memory access requests from said first processing unit directed to said second memory unit and transmitting the memory access requests to said second memory control unit; first access receiving means, operatively connected to said second memory control unit and said first memory unit, for accessing said first memory unit with memory access requests from said second memory control unit and from said first processing unit; and first data transfer means, operatively connected to said first access receiving means, said first memory unit, said first processing unit and said second memory control unit, for transferring data from said second memory unit to said second memory control unit and from said second memory control unit to said first processing unit in dependence upon the access request; and said second memory control unit comprising: a second selecting and transmitting means, operatively connected to said second memory unit and said first access receiving means, for selecting memory access requests from said second processing unit directed to said first processing unit and transmitting the memory access requests to said first access receiving means; second access receiving means, operatively connected to said first selecting and transmitting means and said second memory unit, for accessing said second memory unit with memory access requests from said first selecting and transmitting means and from said second processing unit; and second data transfer means, operatively connected to said second access receiving means, said second memory unit, said second processing unit and said first data transfer means, for transferring data from said first memory unit to said first data transfer means, from said first data transfer means to said second processing unit and from said second memory unit to said second processing unit.

Claim 13

A processing system, comprising: a first multiprocessor system comprising a first processing unit, a first memory control unit operatively connected to said first processing unit and a first memory unit operatively connected to said first memory control unit; a second multiprocessor system comprising a second processing unit, a second memory control unit operatively connected to said second processing unit and said first memory control unit, and a second memory unit operatively connected to said second memory control unit; said first memory control unit comprising: first selecting and transmitting means, operatively connected to said first processing unit and said second memory control unit, for selecting memory access requests from said first processing unit directed to said second memory unit and transmitting the memory access requests to said second memory control unit; first access receiving means, operatively connected to said second memory control unit and said first memory unit, for accessing said first memory unit with memory access requests from said second memory control unit and from said first processing unit; and first data transfer means, operatively connected to said first access receiving means, said first memory unit, said first processing unit and said second memory control unit, for transferring data from said second memory unit to said second memory control unit and from said second memory control unit to said first processing unit in dependence upon the access request; and said second memory control unit comprising: a second selecting and transmitting means, operatively connected to said second memory unit and said first access receiving means, for selecting memory access requests from said second processing unit directed to said first processing unit and transmitting the memory access requests to said first access receiving means; second access receiving means, operatively connected to said first selecting and transmitting means and said second memory unit, for accessing said second memory unit with memory access requests from said first selecting and transmitting means and from said second processing unit; and second data transfer means, operatively connected to said second access receiving means, said second memory unit, said second processing unit and said first data transfer means, for transferring data from said first memory unit to said first data transfer means, from said first data transfer means to said second processing unit and from said second memory unit to said second processing unit.

Claim 14

A processing system as claimed in claim 10, wherein said first memory control unit further comprises a first pipe-line for holding memory access requests from the first processing unit directed to said first memory unit and said first access receiving means comprises a second pipe-line.

Claim 15

A data processor system as claimed in claim 1, wherein each said central processing unit sends access request signals and each said memory control unit includes: a first pipeline for controlling access request signals for the main memory unit connected to said memory control unit; a second pipeline for controlling access request signals for another main memory unit connected to another memory control unit; a first access selecting circuit for selecting a first access request signal from access request signals from each central processing unit connected to said memory control unit and from a second access selecting circuit in said other memory control unit, sending said first access request signal to the first pipeline in said memory control unit, and duplicating and sending said first access request signal to the second pipeline in said other memory control unit; a second access selecting circuit for selecting a second access request signal from access request signals from each central processing unit connected to said memory control unit and sending said second access request signal to the first selecting circuit in said other memory control unit; and a data selecting circuit for selecting read data from the main memory connected to said memory control unit and from the data selecting circuit in said other memory control unit, sending the read data to the central processing unit connected to said memory control unit, and duplicating and sending the read data to the data selecting circuit in said other memory control unit, according to outputs form the first and second pipelines.

Claim 16

A data processor system comprising: first and second memory control units operatively connected to each other; first processor connected to the first memory control unit; second processor connected to the second memory control unit; first main memory unit connected to the first memory control unit; and second main memory unit connected to the second memory control unit, said first memory control unit comprising: first control means for receiving access requests from the first processor and from the second memory control unit, selecting a first access request for the first main memory unit, duplicating and sending said first access request to the second memory control unit and controlling data transfer between the first main memory unit and the first processor; second control means for receiving an access request from the first processor, discriminating access requests for the second main memory unit, and sending access requests for the second main memory unit to the second memory control unit; and third control means for receiving a duplicated access request, and for controlling data transfer between the first main memory unit and the second memory control unit; and said second memory control unit comprising: fourth control means for receiving access requests from the second processor and from the first memory control unit, selecting a second access request for the second main memory unit, duplicating and sending said second access request to the first memory control unit, and controlling data transfer between the second main memory unit and the second processor; fifth control means for receiving an access request from the second processor, discriminating access requests for first the first main memory unit, and sending access requests for the main memory unit to the first memory control unit; and sixth control means receiving a duplicated access request from the first control means, and controlling data transfer between the second main memory unit and the first memory control unit.

Claim 17

A data processor system comprising: first and second memory control units operatively connected to each other; first processor connected to the first memory control unit; second processor connected to the second memory control unit; first main memory unit connected to the first memory control unit; and second main memory unit connected to the second memory control unit, said first memory control unit comprising: first control means for receiving access requests from the first processor and from the second memory control unit, selecting a first access request for the first main memory unit, duplicating and sending said first access request to the second memory control unit and controlling data transfer between the first main memory unit and the first processor; second control means for receiving an access request from the first processor, discriminating access requests for the second main memory unit, and sending access requests for the second main memory unit to the second memory control unit; and third control means for receiving a duplicated access request, and for controlling data transfer between the first main memory unit and the second memory control unit; and said second memory control unit comprising: fourth control means for receiving access requests from the second processor and from the first memory control unit, selecting a second access request for the second main memory unit, duplicating and sending said second access request to the first memory control unit, and controlling data transfer between the second main memory unit and the second processor; fifth control means for receiving an access request from the second processor, discriminating access requests for first the first main memory unit, and sending access requests for the main memory unit to the first memory control unit; and sixth control means receiving a duplicated access request from the first control means, and controlling data transfer between the second main memory unit and the first memory control unit.