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JPS57113166A Expired / Lapsed JP ⏱️ 0.0 years remaining

Data processor

Assignee: Fujitsu Ltd
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Filing: 1980-12-29
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Granted: —
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Expires: 2000-12-29
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Abstract

Abstract PURPOSE:To shorten the time of parallel accessing and to improve processing efficiency, by forming a write control signal for the memory modules of multiple-bank constitution including a bit which instructs writing or write inhibition corresponding to each module. CONSTITUTION:A memory M which has memory modules MDL of multiple-bank BNK constitution is accessed through a memory access controller MCU by a data processor which includes a CPU, a channel device CHP, and a vector processor VPU. Data buses BUS are connected between the controller MCU and data processor, and a write control signal to modules MDL is generated including a byte mark BYM consisting of specified bits, which correspond to a module number for parallel access, in addition to bits (a) and (b) which constitute a store control signal ST for independent access, thereby improving processing efficiency.

Inventors

  • 👤 Hiroshi Tamura
  • 👤 Shoji Nakatani

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 22:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS51139218A Cited
JPS5368922A Cited
JPS54102928A Cited
JPS54122039A Cited

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