Patent US5404326A successfully refreshed from Google Patents.
US5404326A
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Static random access memory cell structure having a thin film transistor load
Assignee: Sony Corp
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Filing: 1993-06-28
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Granted: 1995-04-04
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Expires: 2013-06-28
Abstract
Abstract A semiconductor memory apparatus comprises a flip-flop circuit formed of a pair of inverters formed of driver transistors formed on a semiconductor substrate and having an input and an output coupled to each other in a crossing fashion, and transistors formed on a semiconductor thin film formed on the semiconductor substrate, and a pair of access transistors coupled to drain electrodes of the inverters constructing the flip-flop circuit. In this semiconductor memory apparatus, a coupling capacitance is formed on an overlapping portion in which active layers of the semiconductor thin film transistors and gate electrodes of the semiconductor thin film transistors are overlapped to each other and a part of the overlapping portion in which the coupling capacitance is formed is formed within a contact hole, thereby forming a coupling capacitance between the gate electrode and the drain electrode of the inverters. A soft error, caused by an α-particle or the like, can be prevented by this coupling capacitance. Furthermore, at least an impurity concentration of the drain region of the semiconductor thin film transistor at its portion in which the coupling capacitance is formed is selected to be lower than that of the source region of the semiconductor thin film transistor. Thus, a standby current can be suppressed by suppressing an off-state current of the semiconductor thin film transistor.
Inventors
- 👤 Yutaka Okamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:06
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
208 words
A semiconductor memory apparatus comprising: a flip-flop circuit formed of a pair of driver transistors formed on a semiconductor substrate and having gate, drain and source electrodes, a pair of thin film transistors having drain, source and gate electrodes, and formed on a semiconductor thin film formed on said semiconductor substrate, the drain electrodes of each of said pair of driver transistors coupled to the gate electrodes of the other driver transistor in a crossing fashion; a pair of access transistors formed on said substrate and coupled to said flip-flop circuit and to said drain electrodes of said driver transistors, said semiconductor thin film transistors which are formed on a semiconductor thin film coupled to said driver transistors through a contact hole formed on drain portions of said driver transistors, coupling capacitance formed between overlapping gate electrodes of said semiconductor thin film transistors and said gate electrodes of said driver transistors within said contact hole, and wherein said contact hole is formed so as to couple said gate electrode of said thin film transistor and the gate electrode of said driver transistor and an insulation layer formed between them on side walls and the bottom of said contact hole so as to increase the capacitance between said gates.
Claim 2
Dependent Claim
208 words
A semiconductor memory apparatus comprising: a flip-flop circuit formed of a pair of driver transistors formed on a semiconductor substrate and having gate, drain and source electrodes, a pair of thin film transistors having drain, source and gate electrodes, and formed on a semiconductor thin film formed on said semiconductor substrate, the drain electrodes of each of said pair of driver transistors coupled to the gate electrodes of the other driver transistor in a crossing fashion; a pair of access transistors formed on said substrate and coupled to said flip-flop circuit and to said drain electrodes of said driver transistors, said semiconductor thin film transistors which are formed on a semiconductor thin film coupled to said driver transistors through a contact hole formed on drain portions of said driver transistors, coupling capacitance formed between overlapping gate electrodes of said semiconductor thin film transistors and said gate electrodes of said driver transistors within said contact hole, and wherein said contact hole is formed so as to couple said gate electrode of said thin film transistor and the gate electrode of said driver transistor and an insulation layer formed between them on side walls and the bottom of said contact hole so as to increase the capacitance between said gates.
Claim 3
Dependent Claim
206 words
A semiconductor memory apparatus comprising: a flip-flop circuit formed of a pair of driver transistors formed on a semiconductor substrate and having source, drain and gate electrodes coupled to each other, a pair of thin film transistors with source, drain and gate electrodes formed on a semiconductor thin film on said semiconductor substrate, the drain electrodes of each of said pair of driver transistors coupled to the gate electrodes of the other driver transistor in a crossing fashion; a pair of access transistors coupled to said flip-flop circuit and to said drain electrodes of said driver transistors, said thin film transistors formed of semiconductor thin films laminated on said driver transistors, said gate electrodes of said semiconductor thin film transistors coupled to the drain electrodes of said thin film transistors through an insulation film, and the impurity concentration of at least a portion of said drain regions of said thin film transistors being lower than said source region of said semiconductor thin film transistors, and wherein said drain regions of said thin film transistors have at least two portions with different impurity concentration and with one portion having an impurity concentration which is lower than the impurity concentration of said sources of said thin film transistors.
Claim 4
Dependent Claim
206 words
A semiconductor memory apparatus comprising: a flip-flop circuit formed of a pair of driver transistors formed on a semiconductor substrate and having source, drain and gate electrodes coupled to each other, a pair of thin film transistors with source, drain and gate electrodes formed on a semiconductor thin film on said semiconductor substrate, the drain electrodes of each of said pair of driver transistors coupled to the gate electrodes of the other driver transistor in a crossing fashion; a pair of access transistors coupled to said flip-flop circuit and to said drain electrodes of said driver transistors, said thin film transistors formed of semiconductor thin films laminated on said driver transistors, said gate electrodes of said semiconductor thin film transistors coupled to the drain electrodes of said thin film transistors through an insulation film, and the impurity concentration of at least a portion of said drain regions of said thin film transistors being lower than said source region of said semiconductor thin film transistors, and wherein said drain regions of said thin film transistors have at least two portions with different impurity concentration and with one portion having an impurity concentration which is lower than the impurity concentration of said sources of said thin film transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
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