US5157474A
Expired / Lapsed
US
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Static memory
Assignee: Toshiba Corp
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Filing: 1990-04-10
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Granted: 1992-10-20
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Expires: 2010-04-10
Abstract
Abstract A static memory in which polysilicon thin film transistors serve as load elements in a memory cell, and the gate electrodes of the polysilicon thin film transistors are formed of diffusion regions. In the static memory, high quality uniform TFTS are formed, and the oxidation films of the TFTs can be thin, without using a complex manufacturing technique.
Inventors
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:17
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
127 words
A static memory comprising: a semiconductor substrate; first and second driving MOS transistors of a first channel conductivity type, each having source and drain regions and a gate electrode, the source and drain regions of said first and second driving MOS transistors being formed in said semiconductor substrate; and third and fourth load MOS transistors of a second channel conductively type, each having source and drain regions and a gate electrode, the source and drain regions of said third and fourth load MOS transistors being formed in a polysilicon thin film, the gate electrodes thereof comprising diffusion regions in said semiconductor substrate; wherein channel lengths of said first and second driving MOS transistors are substantially perpendicular to channel lengths of said third and fourth load MOS transistors.
Claim 2
Dependent Claim
127 words
A static memory comprising: a semiconductor substrate; first and second driving MOS transistors of a first channel conductivity type, each having source and drain regions and a gate electrode, the source and drain regions of said first and second driving MOS transistors being formed in said semiconductor substrate; and third and fourth load MOS transistors of a second channel conductively type, each having source and drain regions and a gate electrode, the source and drain regions of said third and fourth load MOS transistors being formed in a polysilicon thin film, the gate electrodes thereof comprising diffusion regions in said semiconductor substrate; wherein channel lengths of said first and second driving MOS transistors are substantially perpendicular to channel lengths of said third and fourth load MOS transistors.
Claim 3
Dependent Claim
244 words
A static memory comprising: first and second memory nodes; a first driving MOS transistor of a first channel conductivity type having a drain diffusion region connected to said first memory node, a source diffusion region connected to a first reference potential, and a gate electrode connected to said second memory node; a second driving MOS transistor of the first channel conductivity type having a drain diffusion region connected to said second memory node, a source diffusion region connected to said first reference potential, and a gate electrode connected to said first memory node; a third MOS transistor of a second channel conductivity type consisting of a polysilicon thin film transistor having a gate electrode formed of the drain diffusion region of said second drive MOS transistor, a source diffusion region connected to a second reference potential and a drain diffusion region connected to said first memory node, a channel length of said third MOS transistor being substantially perpendicular to a channel length of said second driving MOS transistor; and a fourth MOS transistor of the second channel conductivity type consisting of a polysilicon thin film transistor having a gate electrode formed of the drain diffusion region of said first driving MOS transistor, a source diffusion region connected to said second reference potential and a drain diffusion region connected to said second memory node, a channel length of said fourth MOS transistor being substantially perpendicular to a channel length of said first driving MOS transistor.
Claim 4
Dependent Claim
244 words
A static memory comprising: first and second memory nodes; a first driving MOS transistor of a first channel conductivity type having a drain diffusion region connected to said first memory node, a source diffusion region connected to a first reference potential, and a gate electrode connected to said second memory node; a second driving MOS transistor of the first channel conductivity type having a drain diffusion region connected to said second memory node, a source diffusion region connected to said first reference potential, and a gate electrode connected to said first memory node; a third MOS transistor of a second channel conductivity type consisting of a polysilicon thin film transistor having a gate electrode formed of the drain diffusion region of said second drive MOS transistor, a source diffusion region connected to a second reference potential and a drain diffusion region connected to said first memory node, a channel length of said third MOS transistor being substantially perpendicular to a channel length of said second driving MOS transistor; and a fourth MOS transistor of the second channel conductivity type consisting of a polysilicon thin film transistor having a gate electrode formed of the drain diffusion region of said first driving MOS transistor, a source diffusion region connected to said second reference potential and a drain diffusion region connected to said second memory node, a channel length of said fourth MOS transistor being substantially perpendicular to a channel length of said first driving MOS transistor.
Claim 5
Dependent Claim
42 words
The static memory according to claim 2, wherein gate insulating films adjacent the gate electrodes of said third and fourth MOS transistors are formed of thermally-grown films formed on said drain diffusion regions of said second and first driving MOS transistors respectively.
Claim 6
Dependent Claim
53 words
The static memory according to claim 1 wherein said source and drain regions of said first and second driving MOS transistors comprise diffusion regions formed in said semiconductor substrate, said drain regions of said first and second driving MOS transistors respectively comprising said gate electrodes of said third and fourth load MOS transistors.
References Cited (Backward Citations)
US4633438A
Cited
US4920391A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |