High density EEPROM cell array with improved access time and method of manufacture

Claim 1

An electrically-erasable, programmable read-only-memory (EEPROM) array, the EEPROM array comprising: a semiconductor material having a plurality of adjacent segment select regions and a plurality of adjacent array regions arranged so that one array region is located between and adjoins each pair of adjacent segment select regions; a plurality of spaced-apart strips of first field oxide formed on the semiconductor material so that a portion of each strip is formed in each segment select region and in each array region, each pair of adjacent strips of first field oxide in each array region defining an active device region therebetween; a plurality of bit lines formed in the semiconductor material in each pair of adjacent segment select regions and the adjoining array region located therebetween so that a pair of bit lines are formed between and adjacent to each pair of adjacent strips of first field oxide; a layer of second field oxide formed on the semiconductor material over each bit line; a plurality of spaced-apart first channel regions positioned within the semiconductor material in each active device region so that each first channel region is formed between and adjoins the pair of bit lines formed therein; a layer of first gate dielectric material formed on the semiconductor material in each of the array regions, the layer of first gate dielectric material having a plurality of tunnel openings which are positioned so that each tunnel opening overlies a portion of one first channel region; a layer of tunnel dielectric material formed in each tunnel opening of the layer of first gate dielectric material; a plurality of floating gate structures, each floating gate structure formed on the layer of first gate dielectric material over one of the first channel regions, each floating gate structure comprising a layer of first conducting material and an overlying layer of intermediate dielectric material; a plurality of second channel regions positioned within the semiconductor material in each segment select region; a layer of second gate dielectric material formed on the semiconductor material in each of the segment select regions; a plurality of segment select lines formed over the layer of second gate dielectric material orthogonal to the plurality of buried bit lines so that each segment select line overlies a plurality of second channel regions, the portion of each segment select line overlying each second channel region forming a control gate; a plurality of word lines formed orthogonal to the plurality of buried bit lines so that each word line overlies a plurality of floating gate structures; and a plurality of source regions formed in the semiconductor material in each segment select region, each source region being formed between and adjoining one second channel region and one bit line; and a plurality of drain regions formed in the semiconductor material in each segment select region, each drain region adjoining one second channel region on a side opposite to a source region.