Thermal process for implementing the planarization inherent to stacked etch in virtual ground EPROM memories

Claim 1

A method of fabricating a virtual ground EPROM cell in a silicon substrate of P-type conductivity, the method comprising: (a) forming a gate oxide layer on the silicon substrate; (b) forming a first polysilicon layer on the gate oxide layer; (c) forming a first oxide layer on the first polysilicon layer; (d) forming a nitride layer on the first oxide layer; (e) forming a second oxide layer on the nitride layer, thereby to form a composite layer of oxide-nitride-oxide (ONO) and first polysilicon on the gate oxide layer; (f) forming a mask structure to define parallel lines of ONO/poly 1; (g) etching exposed portions of the ONO/poly 1 to define parallel lines of ONO/poly 1; (h) while maintaining the mask structure in place, forming lines of N-type conductivity in the silicon substrate between the parallel lines of ONO/poly 1; (i) removing the mask structure; and (j) performing a differential oxidation to increase the thickness of the second oxide layer while simultaneously forming oxide over the lines of N-type conductivity whereby the subsequent etching of the parallel lines of ONO/poly 1 in a stacked etch step of the method etches only a portion of the oxide formed over the lines of N-type conductivity, thereby avoiding interruption of the N+ bit lines of the EPROM cell.

Claim 2

A method of fabricating a virtual ground EPROM cell in a silicon substrate of P-type conductivity, the method comprising: (a) forming a gate oxide layer on the silicon substrate; (b) forming a first polysilicon layer on the gate oxide layer; (c) forming a first oxide layer on the first polysilicon layer; (d) forming a nitride layer on the first oxide layer; (e) forming a second oxide layer on the nitride layer, thereby to form a composite layer of oxide-nitride-oxide (ONO) and first polysilicon on the gate oxide layer; (f) forming a mask structure to define parallel lines of ONO/poly 1; (g) etching exposed portions of the ONO/poly 1 to define parallel lines of ONO/poly 1; (h) while maintaining the mask structure in place, forming lines of N-type conductivity in the silicon substrate between the parallel lines of ONO/poly 1; (i) removing the mask structure; and (j) performing a differential oxidation to increase the thickness of the second oxide layer while simultaneously forming oxide over the lines of N-type conductivity whereby the subsequent etching of the parallel lines of ONO/poly 1 in a stacked etch step of the method etches only a portion of the oxide formed over the lines of N-type conductivity, thereby avoiding interruption of the N+ bit lines of the EPROM cell.

Claim 10

A method of fabricating a virtual ground EPROM cell in a semiconductor substrate of a first conductivity type, the method comprising the steps of: (a) forming layer of first dielectric material on the semiconductor substrate; (b) forming a layer of conductive material over the first dielectric material; (c) forming a layer of second dielectric material over the conductive material; (d) forming a mask structure over the second dielectric material to define parallel lines of second dielectric material; (e) etching the second dielectric material and the underlying conductive material to provide a plurality of spaced-apart, parallel lines of second insulating material and underlying conductive material; (f) while maintaining the mask structure in place on the parallel lines of second insulating material and underlying conductive material, forming regions of a conductivity type opposite the first conductivity type in the semiconductor substrate between the parallel lines of second insulating material and underlying conductive material; (g) removing the mask structure from the parallel lines of second insulating material and underlying conductive material; and (h) increasing the thickness of the second dielectric material on the parallel lines while simultaneously forming dielectric material over the regions of opposite conductivity type.

Claim 11

A method of fabricating a virtual ground EPROM cell in a semiconductor substrate of a first conductivity type, the method comprising the steps of: (a) forming layer of first dielectric material on the semiconductor substrate; (b) forming a layer of conductive material over the first dielectric material; (c) forming a layer of second dielectric material over the conductive material; (d) forming a mask structure over the second dielectric material to define parallel lines of second dielectric material; (e) etching the second dielectric material and the underlying conductive material to provide a plurality of spaced-apart, parallel lines of second insulating material and underlying conductive material; (f) while maintaining the mask structure in place on the parallel lines of second insulating material and underlying conductive material, forming regions of a conductivity type opposite the first conductivity type in the semiconductor substrate between the parallel lines of second insulating material and underlying conductive material; (g) removing the mask structure from the parallel lines of second insulating material and underlying conductive material; and (h) increasing the thickness of the second dielectric material on the parallel lines while simultaneously forming dielectric material over the regions of opposite conductivity type.