Semiconductor memory having test circuit and test method thereof

Claim 2

A semiconductor memory comprising: a plurality of memory cells which are arranged in a matrix; a plurality of bit lines and a plurality of word lines connected to said plurality of memory cells for performing read/write access of data to said memory cells; a row decoder; a word driver; a sense circuit; a column decoder; a multiplexer for controlling read/write access of data; and a test circuit, said test circuit comprising external terminal means for sending test data and expected value data, simultaneous write means for simultaneously writing the test data from said external terminal means to said plurality of memory cells, and simultaneous comparison means for simultaneously comparing the expected value data supplied from said external terminal means to the test data written in said plurality of memory cells, said simultaneous write means in said test circuit writing the test data to said plurality of memory cells connected to a selected word line, said simultaneous write means being constituted by a plurality of test data write control gates, each gate formed at a respective pair of bit lines to write the test data into said plurality of memory cells connected to said selected word line, the total of said test data write control gates corresponding to all pairs of bit lines in said matrix, and a pair of bit lines being directly connected to said data write control gate, said simultaneous comparison means comparing the expected value data with the test data written in said plurality of memory cells connected to said selected word line, said simultaneous comparison means being constituted by logic circuits receiving a plurality of outputs from a plurality of comparators, each comparator being formed at a respective pair of bit lines, the total of said plurality of comparators corresponding to all pairs of bit lines, and each of said pairs of bit lines being directly connected to a respective one of said comparators.

Claim 3

A memory according to claim 1, wherein main bit lines are provided which are not connected to the memory cells but to the bit lines via controlled switches.

Claim 4

A memory according to claim 1 wherein the expected value data has the same value as the test data or inverted data of the test data.

Claim 5

A memory according to claim 1, wherein said bit lines have a folded bit line connection arrangement with respect to said memory cells.

Claim 6

A memory according to claim 1, wherein said bit lines have an open bit line connection arrangement with respect to said memory cells.

Claim 7

A memory according to claim 1, wherein sense circuits connected to said bit lines are arranged at two sides of the matrix.

Claim 8

A memory according to claim 1, wherein said external terminal means includes independent input and output circuits.

Claim 9

A memory according to claim 1, wherein said external means includes an input/output common circuit.

Claim 10

A memory according to claim 1, wherein said external terminal means also has a function of a data input/output terminal, and wherein the memory further comprises: test mode setting signal generators for detecting level transition timings of fundamental clocks and sending test mode setting signals; and switch means, said switch means connecting said external terminal means not to said multiplexer but to said test circuit, and transmitting the test data and the expected value data to said test circuit upon reception of the test mode setting signals.

Claim 11

A memory according to claim 9, wherein said switch means switches said external terminal means from a data transmission system for said memory cells to said simultaneous write means and said simultaneous comparison means upon reception of the test mode setting signal and a write control signal of the test data.

Claim 12

A memory according to claim 9, wherein the fundamental clocks comprise a row control clock, a column control clock, and a write control clock for said memory cell matrix.

Claim 13

A memory according to claim 9, further comprising latch means between said switch means and said test circuit.

Claim 14

A memory according to claim 1, wherein said memory cells arranged in the matrix comprise a plurality of main memory cells and a plurality of supplementary memory cells for defect remedy, a plurality of bit lines, a plurality of supplementary bit lines, a plurality of word lines and a plurality of supplementary word lines connected to said plurality of main memory cells and supplementary memory cells for performing read/write access of data to said memory cells, and having a supplementary row decoder and supplementary column decoder, a supplementary sense circuit, supplementary multiplexer and supplementary word driver, and further comprises: said simultaneous write means writes the test data in said plurality of main memory cells and supplementary memory cells connected to a selected word line, said plurality of supplementary memory cells connected to a selected supplementary word line, said simultaneous write means being constituted by a plurality of test data write control gates formed at a pair of bit lines and a pair of supplementary bit lines, the total of said test data write control gates corresponding to all pairs of bit lines and all pairs of supplementary bit lines in said matrix, and a pair of bit lines and a pair of supplementary bit lines being directly connected to said test data write control gate, said simultaneous comparison means compares the expected value data with the test data written in said plurality of main memory cells and supplementary memory cells connected to a selected word line and the test-data written in said plurality of supplementary memory cells connected to a selected supplementary word line, said simultaneous comparison means being constituted by logic circuits receiving a plurality of outputs from a plurality of comparators respectively formed at a pair of bit lines and at a pair of supplementary bit lines, the total of said plurality of said comparators corresponding to all pairs of bit lines and all pairs of supplementary bit lines, and each of said pairs of bit lines and each of said pairs of supplementary bit lines being directly connected to a respective one of said comparators.

Claim 15

A memory according to claim 13, wherein said test circuit comprises switching control means for disconnecting a defective memory cell from said simultaneous comparison means and connecting the supplementary memory cell to the corresponding portion.

Claim 16

A memory according to claim 14, wherein said switching control means comprises a storage element, said storage element being arranged to change its storage value when a defect occurs.

Claim 17

A memory according to claim 15, wherein the storage value corresponds to an address of the defective memory cell.

Claim 18

A memory according to claim 13, wherein said external terminal means also has a function of a data input/output terminal, and wherein the memory further comprises: test mode setting signal generators for detecting level transition timings of fundamental clocks and sending test mode setting signals, and switch means, said switch means connecting said external terminals means not to said multiplexer but to said test circuit, and transmitting the test data and the expected value data to said test circuit upon reception of the test mode setting signals.

Claim 19

A memory according to claim 17, further comprising latch means between said switch means and said test circuit.

Claim 20

A memory according to claim 17, wherein said external terminal means includes independent input and output circuits.

Claim 21

A memory according to claim 17, wherein said external terminal means includes a common input/output circuit.

Claim 24

A method according to claim 21, wherein in the test, said peripheral circuit has a highest priority order, and circuits other than said peripheral circuit have the second highest priority order.

Claim 25

A method according to claim 21, wherein in the test, said peripheral circuit is tested first, said test circuit is tested second, and said memory cells are tested last.

Claim 26

A method according to claim 21, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line of said memory cells on the matrix.

Claim 27

A method according to claim 21, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line, a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.

Claim 28

A method according to claim 21, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.

Claim 29

A method according to claim 21, wherein the test data and the expected value data for the test are externally input data.

Claim 30

A method according to claim 21, wherein the test data and the expected value data for the test are data stored in an internal memory element which is externally selected to perform a corresponding test.

Claim 31

A method according to claim 21, wherein the test is divided into a plurality of steps depending on portions to be tested, and a result of each test is checked after each step of the test is completed.

Claim 32

A method according to claim 21, wherein the test is divided into a plurality of steps depending on portions to be tested, and a result of each test is checked during each step of the test.

Claim 33

A method according to claim 21, wherein said memory cells arranged in the matrix comprise a plurality of main memory cells and a plurality of supplementary memory cells for defect remedy, a plurality of bit lines, a plurality of supplementary bit lines, a plurality of word lines and a plurality of supplementary word lines connected to said plurality of main memory cells and supplementary memory cells for performing read/write access of data to said memory cells, and said semiconductor memory further having a supplementary row decoder and supplementary column decoder, a supplementary sense circuit, supplementary multiplexer and supplementary word driver, and further comprises: said simultaneous write means writes the test data in said plurality of main memory cells and supplementary memory cells connected to a selected word line, said plurality of supplementary memory cells connected to a selected supplementary word line, said simultaneous write means being constituted by plurality of test data write control gates, formed at a pair of bit lines and a pair of supplementary bit lines, the total of said test data write control gates corresponding to all pairs of bit lines and all pairs of supplementary bit lines in said matrix, and a pair of bit lines and a pair of supplementary bit lines being directly connected to said test data write control gate, said simultaneous comparison means compares the expected value data with the test data written in said plurality of main memory cells and supplementary memory cells connected to a selected word line and the test data written in said plurality of supplementary memory cells connected to a selected supplementary word line, said simultaneous comparison means being constituted by logic circuits receiving a plurality of outputs from a plurality of comparators, each comparator being formed at a respective pair of bit lines and at a pair of supplementary bit lines, the total of said plurality of said comparators corresponding to all pairs of bit lines and all pairs or supplementary bit lines, and each of said pairs of bit lines and each of said pairs of supplementary bit lines being directly connected to a respective one of said comparators, said method comprising: sequentially testing predetermined portions by said test circuit in a predetermined order and inhibiting subsequent tests when the defect remedy cannot be performed by substituting a defective memory cell with the supplementary memory cell, and simultaneously writing test data in predetermined memory cells connected to bit lines and supplementary bit lines intersecting one word line or one supplementary word line when said main memory cells and said supplementary memory cells serve as objects to be tested, and thereafter, comparing readout data with expected value data to check the memory cells connected to said word line or said supplementary word line.

Claim 34

A method according to claim 31, wherein in the test, said peripheral circuit has a highest priority order, and circuits other than said peripheral circuit have the second highest priority order.

Claim 35

A method according to claim 31, wherein in the test, said peripheral circuit is tested first, said test circuit is tested second, and said memory cells are tested last.

Claim 36

A method according to claim 31, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line of said memory cells on the matrix.

Claim 37

A method according to claim 31, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line, a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.

Claim 38

A method according to claim 31, wherein the test of said peripheral circuit is performed for a portion corresponding to a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.