Patent US5399532A successfully refreshed from Google Patents.
US5399532A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit window etch and planarization
Assignee: AT&T Inc
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Filing: 1992-07-30
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Granted: 1995-03-21
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Expires: 2012-07-30
Abstract
Abstract A method of semiconductor integrated circuit fabrication which provides a tapered window and a smoothed dielectric. A trench is made by etching through patterned photoresist into a dielectric. Then the corners of the trench are smoothed by thermal flow. Next the trench is etched downward by RIE blanket etchback. A window with tapered sides is thereby opened to the substrate and the dielectric is simultaneously smoothed.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chen-Hua D. Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:51
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
152 words
A method of semiconductor integrated circuit fabrication comprising: forming an undoped oxide dielectric upon a silicon substrate, said undopeal oxide dielectric having an etch rate; forming a doped dielectric having an initial thickness, upon said undoped oxide dielectric; said doped dielectric having an etch rate which is greater than the etch rate of said undoped oxide dielectric; etching said doped dielectric material without exposing said undoped oxide dielectric thereby forming a trench with an upper edge and a lower edge; smoothing said upper edge and said lower edge of said trench; and then blanket etching said doped dielectric and said undoped oxide dielectric to deepen said trench, thereby exposing said substrate at the bottom of said deepened trench, the said initial thickness of said doped dielectric being chosen so that a portion of said doped dielectric layer remains above said undoped oxide dielectric away from said trench after said substrate is exposed.
Claim 2
Independent Claim
152 words
A method of semiconductor integrated circuit fabrication comprising: forming an undoped oxide dielectric upon a silicon substrate, said undopeal oxide dielectric having an etch rate; forming a doped dielectric having an initial thickness, upon said undoped oxide dielectric; said doped dielectric having an etch rate which is greater than the etch rate of said undoped oxide dielectric; etching said doped dielectric material without exposing said undoped oxide dielectric thereby forming a trench with an upper edge and a lower edge; smoothing said upper edge and said lower edge of said trench; and then blanket etching said doped dielectric and said undoped oxide dielectric to deepen said trench, thereby exposing said substrate at the bottom of said deepened trench, the said initial thickness of said doped dielectric being chosen so that a portion of said doped dielectric layer remains above said undoped oxide dielectric away from said trench after said substrate is exposed.
Claim 3
Dependent Claim
12 words
The method of claim 1 in which said doped dielectric is BPTEOS.
Claim 4
Dependent Claim
22 words
The method of claim 1 in which said smoothing step is accomplished by heating said dielectric thereby causing said dielectric to flow.
Claim 5
Dependent Claim
26 words
The method of claim 3 in which said smoothing step is performed at a temperature of 800° C.±25° and a time of 3 to 30 minutes.
Claim 6
Dependent Claim
21 words
The method of claim 1 in which said, blanket etching is performed by reactive ion etching utilizing CHF 3 and oxygen.
Claim 7
Dependent Claim
20 words
The method of claim 1 further including the step of filling said trench with conductive material which contacts said substrate.
Claim 8
Dependent Claim
33 words
The method of claim 1 further including the step of forming a silicide layer overlying said substrate and also including the step of filling said trench with conductive material which contacts said silicide.
Claim 9
Dependent Claim
19 words
The method of claim 2 in which the thickness of said BPTEOS is between 0.9 μm and 1.5 μm.
Claim 10
Dependent Claim
18 words
The method of claim 8 in which at least 2000 Å of BPTEOS material remains below said trench.
Claim 11
Dependent Claim
15 words
The method of claim 1 in which said undoped oxide dielectric is formed from TEOS.
Claim 12
Dependent Claim
18 words
The method of claim 10 in which the thickness of said TEOS layer 2 is approximately 1500 Å.
References Cited (Backward Citations)
JPS5683947A
Cited
JPS56116641A
Cited
JPS5766651A
Cited
CA1201582A
Cited
JPS5842254A
Cited
US4743564A
Cited
JPS61237448A
Cited
JPS621232A
Cited
US4807016A
Cited
JPS6337638A
Cited
JPS6365647A
Cited
US4892753A
Cited
JPS63173344A
Cited
US4966865A
Cited
US4879257A
Cited
JPH02125449A
Cited
JPH0247854A
Cited
JPH02140957A
Cited
US4952524A
Cited
US4978420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |