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Patent US5397729A successfully refreshed from Google Patents.
US5397729A
Expired / Lapsed
US
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Method for fabrication of semiconductor device having polycrystalline silicon and metal silicides
Assignee: AKM MANUFACTURING Ltd
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Filing: 1993-06-14
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Granted: 1995-03-14
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Expires: 2013-06-14
Abstract
Abstract A method of fabricating a semiconductor device having a semiconductor substrate, a MOS transistor formed on one surface of the semiconductor substrate, and a capacitor is disclosed. The MOS has a gate electrode with a polycrystalline silicon layer and a metal silicide layer. The capacitor includes a first polycrystalline silicon layer which forms a lower electrode layer, an insulating interlayer, and a second polycrystalline silicon layer which forms an upper electrode, the first and second polycrystalline silicon layers sandwiching the insulating interlayer.
Inventors
- 👤 Sachiro Kayanuma
- 👤 Koji Iki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:09
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D64/00; H10D64/60; H10D64/66; H10D64/667; H10D64/668; H10D1/60; H10D1/68; H10D84/00; H10D84/80; H10D84/811; H10D84/813; H10D84/817; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
175 words
A method for fabricating a semiconductor device comprising the steps of: (a) forming on one surface of a semiconductor substrate a field oxide layer and a gate oxide layer; (b) depositing a first polycrystalline silicon layer; (c) forming an insulating layer over said first polycrystalline silicon layer; (d) depositing a second polycrystalline silicon layer on said insulating layer; (e) etching said second polycrystalline silicon layer outside a portion designated as an upper electrode layer of a capacitor; (f) selectively covering a first mask over said upper electrode layer and its peripheral portion; (g) forming a metal silicide layer; (h) forming a second mask over a portion of said metal silicide layer designated as a gate electrode of a MOS transistor; and (i) etching said first polycrystalline silicon layer and said metal silicide layer to form a gate electrode and a capacitor, said gate electrode comprising a lamination of said first polycrystalline silicon layer and said metal silicide layer, said capacitor comprising a lamination of said first and second polycrystalline silicon layers and said insulating layer.
Claim 2
Independent Claim
175 words
A method for fabricating a semiconductor device comprising the steps of: (a) forming on one surface of a semiconductor substrate a field oxide layer and a gate oxide layer; (b) depositing a first polycrystalline silicon layer; (c) forming an insulating layer over said first polycrystalline silicon layer; (d) depositing a second polycrystalline silicon layer on said insulating layer; (e) etching said second polycrystalline silicon layer outside a portion designated as an upper electrode layer of a capacitor; (f) selectively covering a first mask over said upper electrode layer and its peripheral portion; (g) forming a metal silicide layer; (h) forming a second mask over a portion of said metal silicide layer designated as a gate electrode of a MOS transistor; and (i) etching said first polycrystalline silicon layer and said metal silicide layer to form a gate electrode and a capacitor, said gate electrode comprising a lamination of said first polycrystalline silicon layer and said metal silicide layer, said capacitor comprising a lamination of said first and second polycrystalline silicon layers and said insulating layer.
Claim 3
Dependent Claim
20 words
The method for fabricating a semiconductor device as claimed in claim 1, wherein said first mask is an insulating layer.
Claim 4
Dependent Claim
24 words
The method for fabricating a semiconductor device as claimed in claim 1, wherein said first mask is SiO 2 deposited by a CVD process.
Claim 5
Dependent Claim
23 words
The method for fabricating a semiconductor device as claimed in claim 2, wherein said first mask is SiN deposited by a CVD process.
Claim 6
Dependent Claim
42 words
The method for fabricating a semiconductor device as claimed in claim 2, wherein said metal silicide layers comprises at least one metal silicide selected from the group consisting of WSi, MoSi 2 , TiSi 2 , TaSi 2 and CoSi 2 .
Claim 7
Dependent Claim
41 words
The method for fabricating a semiconductor device as claimed in claim 1, wherein said first polycrystalline silicon layer is doped with impurities in such an amount that said first polycrystalline silicon layer has a sheet resistance of from 30 to 1,000Ω/□.
Claim 8
Independent Claim
193 words
A method for fabricating a semiconductor device comprising the steps of: (a) forming on one surface of a semiconductor substrate a field oxide layer and a gate oxide layer; (b) depositing a first polycrystalline silicon layer; (c) forming an insulating layer over said first polycrystalline silicon layer; (d) depositing a second polycrystalline silicon layer over said insulating layer; (e) etching said second polycrystalline silicon layer outside a portion designated as an upper electrode layer of a capacitor; (f) selectively covering a first mask over said upper electrode layer and the peripheral surface thereof and a portion designated as a resistor, said resistor comprising a single polycrystalline silicon layer; (g) forming a metal silicide layer; (h) forming a second mask over a portion of said metal silicide layer designated as a gate electrode of a MOS transistor; and (i) etching said first polycrystalline silicon layer and said metal silicide layer to form a gate electrode, a capacitor, and a resistor, said gate electrode comprising a lamination of said first polycrystalline silicon layer and said metal silicide layer, said capacitor comprising a lamination of said first and second polycrystalline silicon layers and said insulating interlayer.
Claim 9
Independent Claim
193 words
A method for fabricating a semiconductor device comprising the steps of: (a) forming on one surface of a semiconductor substrate a field oxide layer and a gate oxide layer; (b) depositing a first polycrystalline silicon layer; (c) forming an insulating layer over said first polycrystalline silicon layer; (d) depositing a second polycrystalline silicon layer over said insulating layer; (e) etching said second polycrystalline silicon layer outside a portion designated as an upper electrode layer of a capacitor; (f) selectively covering a first mask over said upper electrode layer and the peripheral surface thereof and a portion designated as a resistor, said resistor comprising a single polycrystalline silicon layer; (g) forming a metal silicide layer; (h) forming a second mask over a portion of said metal silicide layer designated as a gate electrode of a MOS transistor; and (i) etching said first polycrystalline silicon layer and said metal silicide layer to form a gate electrode, a capacitor, and a resistor, said gate electrode comprising a lamination of said first polycrystalline silicon layer and said metal silicide layer, said capacitor comprising a lamination of said first and second polycrystalline silicon layers and said insulating interlayer.
Claim 10
Dependent Claim
79 words
A method for fabricating a semiconductor device as claimed in claim 7, wherein said second polycrystalline silicon layer and said insulating layer are etched; and thereafter said second polycrystalline silicon layer and a portion of said first polycrystalline silicon layer not covered with said second polycrystalline silicon layer are doped with impurities to decrease resistance values of said second polycrystalline silicon layer and said portion of said first polycrystalline silicon layer not covered with said second polycrystalline silicon layer.
Claim 11
Dependent Claim
38 words
A method for fabricating a semiconductor device as claimed in claim 7, wherein said MOS transistor comprising the capacitor and the gate electrode is fabricated in the form of a plurality of units for a switched capacitor filter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |