Method of manufacturing low leakage and long retention time DRAM

Claim 1

The method for making a DRAM MOSFET integrated circuit which includes a cell array region and a peripheral circuits region having low leakage and long retention time in a semiconductor wafer comprising: providing a pattern of gate dielectric and gate electrode structures over said semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of said integrated circuit; using said pattern of gate dielectric and gate electrode structures and ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in said semiconductor wafer wherein said lightly doped regions within said cell array region are to be bit line regions; forming insulator structures upon the sidewall of said pattern of gate dielectric and gate electrode structures; forming a capacitor in electrical contact with certain of said lightly doped regions within said cell array region; forming an interlevel dielectric insulating layer over the surface of the resultant structure; forming openings through said interlevel dielectric insulating layer to said bit line regions of lightly doped regions; forming a highly doped bit line contact to said bit line regions; heating the structure at about 800°-1000° C. to anneal out the ion implantation damage in said lightly doped regions caused by the ion implantation into said lightly doped regions and to cause outdiffusion from said doped capacitor node layer and said doped bit line contact layer to form a highly doped capacitor node contact and highly doped bit line contact, respectively within said lightly doped regions whereby said low leakage and long retention time are the resulting circuit characteristics; forming openings to the desired said lightly doped regions of said peripheral circuits; ion implanting highly doped conductivity imparting dopants of said second and opposite conductivity through said openings to form highly doped source/drain regions of said second and opposite conductivity; and making electrical contact to said peripheral circuits through said openings to complete said DRAM MOSFET integrated circuit.

Claim 2

The method for making a DRAM MOSFET integrated circuit which includes a cell array region and a peripheral circuits region having low leakage and long retention time in a semiconductor wafer comprising: providing a pattern of gate dielectric and gate electrode structures over said semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of said integrated circuit; using said pattern of gate dielectric and gate electrode structures and ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in said semiconductor wafer wherein said lightly doped regions within said cell array region are to be bit line regions; forming insulator structures upon the sidewall of said pattern of gate dielectric and gate electrode structures; forming a capacitor in electrical contact with certain of said lightly doped regions within said cell array region; forming an interlevel dielectric insulating layer over the surface of the resultant structure; forming openings through said interlevel dielectric insulating layer to said bit line regions of lightly doped regions; forming a highly doped bit line contact to said bit line regions; heating the structure at about 800°-1000° C. to anneal out the ion implantation damage in said lightly doped regions caused by the ion implantation into said lightly doped regions and to cause outdiffusion from said doped capacitor node layer and said doped bit line contact layer to form a highly doped capacitor node contact and highly doped bit line contact, respectively within said lightly doped regions whereby said low leakage and long retention time are the resulting circuit characteristics; forming openings to the desired said lightly doped regions of said peripheral circuits; ion implanting highly doped conductivity imparting dopants of said second and opposite conductivity through said openings to form highly doped source/drain regions of said second and opposite conductivity; and making electrical contact to said peripheral circuits through said openings to complete said DRAM MOSFET integrated circuit.

Claim 12

The method for making a DRAM integrated circuit having a cell array composed of MOSFET devices and associated stacked capacitors, and peripheral circuits wherein there is low leakage and long retention time in said cell array comprising: providing a pattern of gate dielectric and gate electrode structures over a semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of said integrated circuit; using said pattern of gate dielectric and gate electrode structures and ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in said semiconductor wafer wherein said lightly doped regions within said cell array region to be capacitor node regions and bit line regions; forming insulator structures upon the sidewall of said pattern of gate dielectric and gate electrode structures; forming a stacked capacitor in electrical contact with capacitor node regions of said lightly doped regions within said cell array region; said capacitor includes a doped polysilicon node layer of the said second and opposite conductivity, a capacitor dielectric, and a doped polysilicon plate layer; forming an interlevel dielectric insulating layer over the surface of the resultant structure; forming openings through said interlevel dielectric insulating layer to said bit line regions of lightly doped regions; forming a highly doped polycide bit line contact to said bit line regions; heating the structure at about 800°-1000° C. to anneal out the ion implantation damage in said lightly doped regions caused by the ion implantation into said lightly doped regions and to cause outdiffusion from said doped capacitor node layer and said doped bit line contact layer to form a highly doped node contact and highly doped bit line contact, respectively within said lightly doped regions whereby said low leakage and long retention time are the resulting circuit characteristics; forming openings to the desired said source and drain regions of said peripheral circuits; ion implanting highly doped conductivity imparting dopants of said second and opposite conductivity through said openings to form highly doped source/drain regions of said second and opposite conductivity; and making electrical contact to said peripheral circuits through said openings to complete said DRAM MOSFET integrated circuit.

Claim 13

The method for making a DRAM integrated circuit having a cell array composed of MOSFET devices and associated stacked capacitors, and peripheral circuits wherein there is low leakage and long retention time in said cell array comprising: providing a pattern of gate dielectric and gate electrode structures over a semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of said integrated circuit; using said pattern of gate dielectric and gate electrode structures and ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in said semiconductor wafer wherein said lightly doped regions within said cell array region to be capacitor node regions and bit line regions; forming insulator structures upon the sidewall of said pattern of gate dielectric and gate electrode structures; forming a stacked capacitor in electrical contact with capacitor node regions of said lightly doped regions within said cell array region; said capacitor includes a doped polysilicon node layer of the said second and opposite conductivity, a capacitor dielectric, and a doped polysilicon plate layer; forming an interlevel dielectric insulating layer over the surface of the resultant structure; forming openings through said interlevel dielectric insulating layer to said bit line regions of lightly doped regions; forming a highly doped polycide bit line contact to said bit line regions; heating the structure at about 800°-1000° C. to anneal out the ion implantation damage in said lightly doped regions caused by the ion implantation into said lightly doped regions and to cause outdiffusion from said doped capacitor node layer and said doped bit line contact layer to form a highly doped node contact and highly doped bit line contact, respectively within said lightly doped regions whereby said low leakage and long retention time are the resulting circuit characteristics; forming openings to the desired said source and drain regions of said peripheral circuits; ion implanting highly doped conductivity imparting dopants of said second and opposite conductivity through said openings to form highly doped source/drain regions of said second and opposite conductivity; and making electrical contact to said peripheral circuits through said openings to complete said DRAM MOSFET integrated circuit.